Parameter Extraction Procedure Research Articles

(Digital Presentation) Temporal Evolution of the Threshold Voltage in Organic Thin Film Memory Transistors

We present a procedure to monitor the temporal evolution of the trapped charge in floating gates of organic thin film transistors (OTFTs) based memories in dynamic regimes. The potential applications of organic semiconductors in flexible and wearable electronics and their known features such as low-temperature and solution fabrication make the OTFTs be considered as candidates also in the field of non-volatile memories. Past efforts have been devoted on the preparation and optimization of floating gates [1]. In the present work, we focus on the modelling of this kind of devices, in particular, on a model for the threshold voltage useful in dynamic experiments, such as hysteresis and transient regimes. The information extracted from the modelling and simulation of these devices can be related to technological parameters with the objective of finding a better memory design.Current-voltage curves impacted by hysteresis are usually reproduced assuming the threshold voltage to be constant or piecewise constant. Nevertheless, despite positive outcomes [2], this is not a precise approach since it does not consider the actual temporal evolution of the threshold voltage. Thus, a time dependent threshold voltage is mandatory in order to interpret hysteresis phenomena and transient experiments, which in turn can be associated to trapping and de-trapping mechanisms over time.In this work, a model that describes the evolution of the threshold voltage with the time, which is linked to the variation of the trapped charge in the channel, is proposed.The evolution of the trapped charge is described with a first-order linear differential equation with a term controlled by a time constant t, and another term, similar to the generation term in a typical continuity equation, which is proportional to the drain current flowing through the transistor channel. This model is introduced in a compact model previously developed for OTFTs that include contact effects [3–6]. The resulting model is combined with an evolutionary parameter extraction procedure, which is applied to experimental current–voltage curves taken from the literature that show both contact and hysteresis effects [7]. Figures (a) and (b) show the best fitting of our calculations (solid lines) and experimental output and transfer characteristics (symbols), respectively, of a pentacene-based organic thin film memory transistor using poly (methyl methacrylate) (PMMA) as the insulator [7]. Figures (c) and (d) show the time evolution of the threshold voltage during the experiments (a) and (b), respectively.The authors acknowledge support from the project PID2022-139586NB-44 funded by MCIN/AEI/10.13039/501100011033 and by European Union NextGenerationEU/PRTR.

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

Compact modeling of hysteresis in organic thin-film transistors

In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics.

Superellipse model: An accurate and easy-to-fit empirical model for photovoltaic panels

The accurate representation of the photovoltaic (PV) characteristic curves especially at maximum power point (MPP) are essential for the real-time performance evaluation of PV panels. Over the years, equivalent circuit models which are based on the conversion behavior of PV panels have been the only approach employed in its modeling, simulation, and analysis. However, since the resulting I–V characteristic equation is inherently nonlinear and implicit, the full range enumeration of the PV characteristic curves is usually obtained in a complicated way. Thus, this paper proposes a novel empirical model for modeling and analysis of PV panels. Due to the unique similarities between the geometric shapes of a superellipse and the graphical characteristics of the I–V curve, an explicit mathematical correlation describing the behavior of PV panels can be established. By outlining a step-by-step procedure, the parameter extraction procedures are illustrated. As a result, the straightforward description of the full-range parameter fitting extraction of the I–V curve is greatly simplified. To validate the superiority of the proposed model over the conventional single-diode model, the model accuracy is evaluated according to the IEC EN 50530 standard. The simulation results revealed that irrespective of PV panel specification, cell material, and ambient conditions, the proposed empirical model maintains a low absolute current and power errors within the vicinity of MPP.

Straightforward bias- and frequency-dependent small-signal model extraction for single-layer graphene FETs

We propose an explicit small-signal graphene field-effect transistor (GFET) parameter extraction procedure based on a charge-based quasi-static model. The dependence of the small-signal parameters on both gate voltage and frequency is precisely validated by high-frequency (up to 18 GHz) on-wafer measurements from a 300 nm device. These parameters are studied simultaneously, in contrast to other works which focus exclusively on few. Efficient procedures have been applied to GFETs for the first time to remove contact and gate resistances from the Y-parameters. The use of these methods yields straightforward equations for extracting the small-signal model parameters, which is extremely useful for radio-frequency circuit design. Furthermore, we show for the first time experimental validation vs. both gate voltage and frequency of the intrinsic GFET non-reciprocal capacitance model. Accurate models are also presented for the gate voltage-dependence of the measured unity-gain and maximum oscillation frequencies as well as of the current and power gains.

Semi-Analytical Method for Determination of Air Bridge Interconnect for GaAs-Based p-i-n Diode

Semi-analytical method for the determination of extrinsic and intrinsic model parameters for GaAs-based p-i-n diode is presented in this article. The main advantage is that the air-bridge interconnect inductance is regarded as an independent element and can be distinguished from the feedline effect. The detail model parameters extraction procedure is proposed, and the corresponding closed-form expressions are derived. Good agreement is obtained between the simulated and measured S-parameters up to 110 GHz to verify the validity of the approach.

Measurement of Pipe and Fluid Properties With a Matrix Array-Based Ultrasonic Clamp-On Flow Meter.

Current ultrasonic clamp-on flow meters consist of a pair of single-element transducers that are carefully positioned before use. This positioning process consists of manually finding the distance between the transducer elements, along the pipe axis, for which maximum signal-to-noise ratio (SNR) is achieved. This distance depends on the sound speed, thickness, and diameter of the pipe and on the sound speed of the liquid. However, these parameters are either known with low accuracy or completely unknown during positioning, making it a manual and troublesome process. Furthermore, even when sensor positioning is done properly, uncertainty about the mentioned parameters, and therefore on the path of the acoustic beams, limits the final accuracy of flow measurements. In this research, we address these issues using an ultrasonic clamp-on flow meter consisting of two matrix arrays, which enables the measurement of pipe and liquid parameters by the flow meter itself. Automatic parameter extraction, combined with the beam-steering capabilities of transducer arrays, yields a sensor capable of compensating for pipe imperfections. Three parameter extraction procedures are presented. In contrast to similar literature, the procedures proposed here do not require that the medium be submerged nor do they require a priori information about it. First, axial Lamb waves are excited along the pipe wall and recorded with one of the arrays. A dispersion curve-fitting algorithm is used to extract bulk sound speeds and wall thickness of the pipe from the measured dispersion curves. Second, circumferential Lamb waves are excited, measured, and corrected for dispersion to extract the pipe diameter. Third, pulse-echo measurements provide the sound speed of the liquid. The effectiveness of the first two procedures has been evaluated using simulated and measured data of stainless steel and aluminum pipes, and the feasibility of the third procedure has been evaluated using simulated data.

Space-Mapping Based Automatic Design of SIW-Based Directional Coupler With Arbitrary Power Ratio

In this paper, an automatic design method allowing efficient design of substrate integrated waveguide (SIW) directional coupler with any given power ratio between 3 dB and 20 dB has been proposed. Due to excessive electromagnetic (EM) simulation time of SIW structure, the space mapping technique is exploited to accelerate the design process. An EM-simulation based dielectric rectangular waveguide (RWG) model acts as the surrogate to reduce the simulation time. A two-stage optimization scheme including a differential evolution (DE) algorithm and a Nelder-Mead (NM) simplex algorithm is used to obtain initial surrogate design. Suitable objective functions are proposed for surrogate optimization and for parameter extraction procedure of space mapping technique. Our proposed method is verified with an X band SIW directional coupler with four different power ratio designs, which are 3dB, 10dB, 15dB and 20dB. The experimental results confirm the effectiveness and efficiency of the method.

Physics-Based Trench-Gate Field-Stop IGBT Modeling With Optimization-Based Parameter Extraction for Device Parameters

As a classical insulated gate bipolar transistor (IGBT) structure, the trench-gate field-stop (FS) IGBT has been widely used. For more convenient application, physics-based trench-gate FS IGBT models have received great attentions due to its effectiveness in simulating key device properties. However, current IGBT modeling studies for this popular IGBT chip seldom investigate the depletion layer behavior under the trench-gate structure. This article first derives the physics-based miller capacitance formula for the trench-gate structure according to finite element method (FEM) simulation. Another haunting issue for these physics-based IGBT models is that the intrinsic device parameters are difficult to be extracted appropriately. Thus, an FEM FS IGBT model is established in Sentaurus TCAD as the benchmark. Then, an improved parameter extraction procedure for a Fourier-series-based (FSB) IGBT model is proposed based on the improved miller capacitance formula. By the particle swarm optimization algorithm, key device parameters for the FSB IGBT model can be successfully extracted by fitting the simulated waveforms to those by FEM simulation at a randomly selected turn-off operating condition. Parameters extracted through the proposed procedure using the FSB IGBT model with the improved miller capacitance formula are very close to the device parameters of the FEM model. More importantly, the reliability and the robustness of the extracted parameters are further validated by comparing the waveforms of FSB model with those of FEM model at different operating conditions.

Improved Hybrid Parameters Extraction of a PV Module Using a Moth Flame Algorithm

The identification of actual photovoltaic (PV) model parameters under real operating condition is a crucial step for PV engineering. An accurate and trusted model depends mainly on the accuracy of the model parameters. In this paper, an accurate and enhanced methodology is intended for PV module parameters extraction in outdoor conditions. The proposed methodology combines numerical methods and analytical formulations of the one diode model to derive the five unknown parameters in any operating condition of irradiance and temperature. First, the measured I-V curves at a random weather condition are translated to standard test conditions (i.e., G = 1000 W/m2, T = 25 °C), using translation equations. The second step consists of using an optimization algorithm namely the moth flame algorithm (MFO) to find out the five parameters at standard test conditions. Analytical formulations, at a random irradiance and temperature, are then used to express the unknown parameters at any irradiance and temperature. The proposed approach is validated under outdoor conditions against measured I-V curves at different irradiances and temperatures. The validation has also been performed under dynamic operation where the measured maximum power point coordinates (MPP) are compared to the predicted maximum power points. The obtained results from the adopted hybrid methodology confirm the accuracy of the parameter extraction procedure.

Datasheet-Driven Compact Model of Silicon Carbide Power MOSFET Including Third-Quadrant Behavior

This article presents a simulation model of silicon carbide (SiC) power MOSFET that accurately predicts both the static and dynamic third-quadrant behavior without compromising the first-quadrant's accuracy. Unlike existing models, this model features an asymmetric third-quadrant behavior for MOSFET characteristics necessary for the accurate synchronous rectifier simulations. Moreover, it includes the gate-dependent body diode behavior, essential for the accurate prediction of freewheeling high-side device behavior in half-bridge configurations with significant gate voltage oscillation. The model also includes reverse recovery characteristics for the accurate overshoot and power loss prediction. Despite having these added features, the model demonstrates good convergence and efficiency due to the replacement of conditional piecewise equations with continuous ones consisting of weighted variables. The model's convergence capability and efficiency have been verified by simulating a five-level cascaded H-bridge multilevel inverter. The model's superior efficiency and accuracy have been validated by comparing it with an established SiC power MOSFET model. Also, an easy-to-follow parameter extraction procedure is documented that only requires data commonly available in commercial datasheets for broader utility. Considering accuracy, efficiency, and convenience, the model is useful for all power electronics converter applications.

A Novel Power Loop Parasitic Extraction Approach for Paralleled Discrete SiC MOSFETs on Multilayer PCB

Paralleled discrete SiC MOSFETs lead to high current capability at low costs. Current sharing is a critical issue for paralleling design with significant impacts on switching losses, current stress, and reliability. The mismatches in power loop caused by parasitic components are one of the main causes for unbalanced currents, which need to be fully extracted and compensated for a well-balanced design. Discrete SiC MOSFETs are usually mounted on a multilayer PCB. The power loop parasitic extraction for such a system needs to deal with current sharing among paralleled devices and multilayer current path coupling effects on PCB. With the two effects mixing together, it is difficult to extract the parasitic components for a single branch from such a multidimensional network. State-of-the-art approaches fail to solve the two issues simultaneously or require very strong computation capability. A novel parasite-specific numerical model is created to reveal the unbalanced components in the power loops. A multiport network with multi-input–multioutput (MIMO) analysis is applied to pursue the correlations between branch currents and parasitic elements in both steady-state process and oscillation process. A four-step parameter extraction procedure is introduced to capture the specific parasitics corresponding to particular current mismatch processes. A double-pulse test (DPT) prototype with two paralleled SiC devices is adopted to demonstrate the proposed approach with artificially inserted mismatches. The proposed method achieves excellent accuracy in parameter extractions. The extraction error is only 2.2% for parasitic inductances and less than 5.6% for resistances and capacitances.

A Compact Memristor Model for Neuromorphic ReRAM Devices in Flux-Charge Space

In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology.

Behavioral Model of Silicon Photo-Multipliers Suitable for Transistor-Level Circuit Simulation

Silicon Photomultipliers (SiPMs) are photo-electronic devices able to detect single photons and permit the measurement of weak optical signals. Single-photon detection is accomplished through high-performance read-out front-end electronics whose design needs accurate modeling of the photomultiplier device. In the past, a useful model was developed, but it is limited to the device electrical characteristic and its parameter extraction procedure requires several measurement steps. A new silicon photomultiplier model is proposed in this paper. It exploits the Verilog-a behavioral language and is appropriate to transistor-level circuit simulations. The photon detection of a single cell is modeled using the traditional electrical model. A statistical model is included to describe the silicon photomultiplier noise caused by dark-count or after-pulsing effects. The paper also includes a procedure for the extraction of the model parameters through measurements. The Verilog-a model and the extraction procedure are validated by comparing simulations to experimental results.

An analytic method for parameter extraction of InP HBTs small-signal model

PurposeHigh-speed Indium Phosphide (InP) HBTs have been widely used to design high-speed analog, digital and mixed-signal integrated circuits. The purpose of this study is to propose a new parameter extraction procedure for determining an improved T-topology small-signal equivalent circuit of InP heterojunction bipolar transistors (HBTs).Design/methodology/approachThe alternating current crowding effect is considered through adding the intrinsic base capacitance in the small-signal equivalent circuit. All of the circuit parameters are extracted directly without using any approximation.FindingsThe extraction technique is more easily understood and clearer than other extraction methods, as the equations are derived from the S-parameters by peeling peripheral elements from small-signal models to get reduced ones and extracting each equivalent-circuit parameter using each equation.Originality/valueTo validate the presented parameter extraction technology, an n-p-n emitter-up InP HBT was analyzed adopting the method. Excellent agreement between measured and modeled S-parameters is obtained up to 40 GHz.

Identification of power PIN diode design parameters: Circuit and device-based simulation approach

This paper aims to present a detailed systematic approach to identify the main design parameters of PIN power diodes. Firstly, the diode physical parameters are initialized using simple analytical equations. The second phase is the optimization of the diode parameters considering PSPICE circuit simulation where an electro-thermal physically based circuit model is utilized depending on a series of dynamic and static measurements. The final optimization step is carried out by using TCAD simulations. First, the diode extracted parameters are used to virtually fabricate the diode by using a process simulator. Then, using the output of the process simulator, a device simulator is used to get the desired output that is validated against experimental data. Three case studies for different power diodes are presented showing a good agreement between circuit/device simulation results and measurements. The presented methodology provides high accuracy like TCAD-based parameter extraction procedure with less time. In addition, it gives higher accuracy than the widely used circuit-based parameter extraction technique.

Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems

This review paper reports the prerequisites of a monolithic integrated terahertz (THz) technology capable of meeting the network capacity requirements of beyond-5G wireless communications system (WCS). Keeping in mind that the terahertz signal generation for the beyond-5G networks relies on the technology power loss management, we propose a single computationally efficient software design tool featuring cutting-edge optical devices and high speed III–V electronics for the design of optoelectronic integrated circuits (OEICs) monolithically integrated on a single Indium-Phosphide (InP) die. Through the implementation of accurate and SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact models of uni-traveling carrier photodiodes (UTC-PDs) and InP double heterojunction bipolar transistors (DHBTs), we demonstrated that the next generation of THz technologies for beyond-5G networks requires (i) a multi-physical understanding of their operation described through electrical, photonic and thermal equations, (ii) dedicated test structures for characterization in the frequency range higher than 110 GHz, (iii) a dedicated parameter extraction procedure, along with (iv) a circuit reliability assessment methodology. Developed on the research and development activities achieved in the past two decades, we detailed each part of the multiphysics design optimization approach while ensuring technology power loss management through a holistic procedure compatible with existing software tools and design flow for the timely and cost-effective achievement of THz OEICs.

Unified electrical model for the contact regions of staggered Thin Film Transistors

In this work, we propose an unified compact model, which includes the effects of both source and drain contact regions, to describe the electrical characteristics of staggered thin film transistors (TFTs). The model is based on a generic drift analytical expression that describes the intrinsic channel of the transistor. Despite the distributed two-dimensional nature of the contacts in staggered configurations, two-terminal components are usually preferred to model the source and drain contact regions. In this regard, a model based on versatile simple expressions that describe the current–voltage relations of both contact regions are proposed in this work. These expressions are based on the physics underlying a metal–organic-metal structure. They can be adapted to different transport conditions, such as Ohmic, space-charge-limited transport or Schottky-like contacts. This adaptation is controlled with the value of a single parameter that modifies the concavity or convexity of these expressions. The model works together with an evolutionary parameter extraction procedure, presented in a previous work for TFTs with negligible drain contact effects, and adapted here to this proposed model for staggered transistors. The results of the model and the evolutionary procedure have been validated with published experimental data of different TFTs, mostly organic thin film transistors (OTFTs). The model and evolutionary procedure agrees with other procedures tested successfully in the literature which were defined to cope with specific kinds of contacts in the TFTs. In this regard, our model and evolutionary parameter extraction procedure unify these previous procedures. • Compact model for the electrical characteristics of staggered TFTs. • Versatile current–voltage model for source and contact regions. • Unified model for space-charge-limited and Schottky-limited contacts. • Single short-channel transistor parameter extraction method. • Evolutionary parameter extraction method.

Extraction of Mobility Degradation and Source-and-Drain Resistance in MOSFETs

A MOSFET model parameters extraction procedure that overcomes the difficulties of separating the effects of source-and-drain series resistance and mobility degradation factor is presented. Instead of the conventional direct fitting, the present procedure involves the use of indirect bidimensional fitting of the source-to-drain resistance of a single device, as obtained from the below-saturation output characteristics measured at several above-threshold gate voltages. The procedure is verified with a simulated long channel FinFET device with externally added resistances and is later applied to experimental planar bulk DRAM MOSFET devices with channel lengths ranging from 0.23μm to 2.0μm. The procedure is shown to be advantageous in terms of computational efficiency and it is appropriate even with high values of externally added series resistances. For the case of devices with various channel lengths, the accuracy of the procedure is improved if the value of RSD is extracted from the shortest channel length. This value of RSD could be used for extracting the other parameters for devices with longer channel.

PSPICE compact model for power MOSFET based on manufacturer datasheet

In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.