Parallel Prefix Structures Research Articles

FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design

FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design

Hybrid Brent Kung Adder with Modified Sum Generator For Energy Efficient Applications

The demand for high-speed and energy-efficient adders in modern portable applications has drastically increased in recent decades. The existing adders have achieved high speed due to their parallel prefix structure, but it consumes more power for wide operands. The proposed Hybrid Brent Kung-Modified Sum Generator (HBK-MSG) achieved high speed due to the usage of Brent Kung (BK) adder and consumes low power with the help of MSG unit. This hybrid adder architecture is applicable for larger operands. It also uses two different structures of sum generators which compute the added result of the operands by incorporating the complement of the carriers. It is designed and simulated using Xilinx ISE 13.2 and it is coded in Verilog HDL. The performance of the proposed HBK-MSG adder is analyzed by measuring area, delay and power consumption. The proposed 64-bit HBK MSG adder reduces the energy consumption by 62.98%, 48.05%, 33.09%, 28.12% and delay by 63.54%, 48.46%, 34.58%, 28.15% when compared with the existing adder designs such as RCA, CSLA, PPF/CSSA_4 and hybrid adder.

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

A Delay Efficient Hybrid Parallel Prefix Variable Latency CSKA Based Multi-Operand Adder with Optimized 5:2 Compressor and Skip Logic

In this paper, a delay efficient multi-operand adder (MOA) is introduced by considering the compression logic and variable latency carry skip adder (VL-CSKA). Here, an optimized 5:2 compressor is initially used to increase the speed of MOA by reducing the number of operands before giving as input to VL-CSKA. Also, the VL-CSKA is modified by replacing the carry propagation with complementary complex gates (CCG) and nucleus stage with improved parallel prefix structure for increasing the speed with fewer components. The delay, area, power, and logic depth of the proposed hybrid parallel prefix VL-CSKA (HPP-VL-CSKA) is also reduced by modifying the group Propagate-Generate (PG) logic in the parallel prefix structure. Also, a new circuit for XOR/XNOR gate is used for the reduction of the delay and power consumption significantly. The synthesis result shows that the suggested adder design overtakes the existing adders by consuming only 5953 area, 1.763power, 1.251fJ and 3516.63 ADP for 20 number of operands, each with 32 bit inputs.

Sum Propagate Adders

Binary adders are present in every digital computer system. Even if their structure has evolved significantly over the last decades following the progress in logic and circuit design, the scaling of implementation technologies, and the improvement of logic synthesis tools, the fundamental carry-propagation algorithm that guides their operation remains unchanged. This work takes a different path and explores the possibility of performing addition by propagating directly the sum bits of previous bit positions instead of carries. The transformation of binary carry-propagate addition to an equivalent sum propagate addition opens up a whole new design space that spans from ripple-sum to sum-lookahead adders. New parallel-prefix structures that follow the sum-propagation paradigm are presented using a newly introduced associative prefix operator. Sum-propagate and carry-propagate adders have asymptotically the same area and delay complexity. In practice, however, carry propagate adders exhibit better characteristics when implemented in currently established implementation technologies. This gap is expected to reduce in the future using multiple-independent-gate transistors that are promising functionality-enhanced beyond CMOS device technologies, and allow the cost-efficient implementation of AND-XOR operations involved in sum-propagate adders.

Design and Analysis of 32 bit R evers e C onverter based on low power Parallel Prefix A dder

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo $2^{n} + 1$ Multiplier

The modulo $2^{n} + 1$ multiplier is the bottleneck of a wide range of applications from residue number system arithmetic to cryptography. Recently, with demand for low-power and energy-efficient designs, the radix-8 Booth recoding has been considered to derive modulo $2^{n} + 1$ multipliers. This brief presents two novel methods to increase the performance and improve the efficiency of radix-8 modulo $2^{n} + 1$ multipliers. The first technique is a method to significantly reduce the amount of bias terms that need to be handled. The second technique is a new hard multiple generator based on a parallel-prefix structure that computes only for odd positions; it results in a lightweight parallel-prefix adder for the computation of the triple of a number with significant area-saving and improved fan-out. The implementation results based on the TSMC 65-nm technology show improvements of at least 27% and up to 57% in the area–time2 product when compared with the recently proposed radix-8 multiplier.

Efficient signed-digit-to-canonical-signed-digit recoding circuits

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2's complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

Area Efficient Sparse Modulo 2<sup>n</sup> - 3 Adder

This paper presents area efficient architecture of modulo 2n - 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2n - 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log2n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Given bit-width n and level (L) restriction, our algorithm excels the existing algorithms in minimizing the size of the prefix graph. We also prove its size-optimality when n is a power of two and L= log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> . Besides prefix graph size optimization and having the best performance-area trade-off, our approach, unlike existing techniques, can 1) handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and 2) generate several feasible solutions that minimize the objective function. Generating several size-optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial high-performance design.

Implementation of Fir Filter Using a Novel modulo Adder for 2n - 2 k -1 Residue Number System

Modular adder is used in Residue Number System (RNS) addition. Moduli set with the form of 2 n -2 k - 1(1≤ k≤ n-2) can offer excellent balance among the RNS channels for multi-channel RNS processing. In this paper, a Finite Impulse Response (FIR) filter using a novel algorithm and its Very Large Scale Integration (VLSI) implementation structure are proposed for modulo 2 n -2 k -1 adder. In the Modular adder algorithm, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Any existing parallel prefix structure can be used in the novel modulo adder. Thus, we can get flexible tradeoff between area and delay. This paper presents FIR filter implementation with modulo 2 n -2 k -1 adder and n +1. These2 n -1 and 2 n +1 adders are based on parallel prefix and carry correction respectively. Some modulo 2 n -2 n-2 -1 adder based on the technique of carry offset, which is only required to obtain the carry information of A+B. In order to find the carries for addition each carry is modified to the utmost carry(4). By using carry computation,the block corrects the carries further in the proposed modulo adder. In this paper, the modulo adder 2 n -2 k -1 is based on the carry correction and parallel prefix addition is proposed. This modulo adder is divided into four units pre-processing unit, the prefix computation unit, the carry correction unit, and the sum computation unit. This paper is organized as follows: section II describes the RNS background and arithmetic operation. Section III describesthe novelmodulo2 n -2 k -1 adder and it's self-testing. Section IV describesthe application of modulo adder in FIR filter. In section V simulation results and comparisons are presented and in section VI conclusion are listed.

Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

We present a new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells. Our comparator exploits a novel scalable parallel prefix structure that leverages the comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. This method reduces dynamic power dissipation by eliminating unnecessary transitions in a parallel prefix structure that generates the N-bit comparison result after (log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> N)+(log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sub> N)+4 CMOS gate delays. Our comparator is composed of locally interconnected CMOS gates with a maximum fan-in and fan-out of five and four, respectively, independent of the comparator bitwidth. The main advantages of our design are high speed and power efficiency, maintained over a wide range. Additionally, our design uses a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth. HSPICE simulation for a 64-b comparator shows a worst case input-output delay of 0.86 ns and a maximum power dissipation of 7.7 mW using 0.15- μm TSMC technology at 1 GHz.

A Novel Modulo $2^{n}-2^{k}-1$ Adder for Residue Number System

Modular adder is one of the key components for the application of residue number system (RNS). Moduli set with the form of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> -1 (1 ≤ k ≤ n-2) can offer excellent balance among the RNS channels for multi-channels RNS processing. In this paper, a novel algorithm and its VLSI implementation structure are proposed for modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> -1 adder. In the proposed algorithm, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Any existing parallel prefix structure can be used in the proposed structure. Thus, we can get flexible tradeoff between area and delay with the proposed structure. Compared with same type modular adder with traditional structures, the proposed modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> -1 adder offers better performance in delay and area.

High-speed parallel-prefix VLSI Ling adders

Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. A novel framework is introduced, which allows the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of implementation compared to the parallel-prefix structures proposed for the traditional definition of carry lookahead equations and reduces the fanout requirements of the design. Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.