Abstract
The demand for high-speed and energy-efficient adders in modern portable applications has drastically increased in recent decades. The existing adders have achieved high speed due to their parallel prefix structure, but it consumes more power for wide operands. The proposed Hybrid Brent Kung-Modified Sum Generator (HBK-MSG) achieved high speed due to the usage of Brent Kung (BK) adder and consumes low power with the help of MSG unit. This hybrid adder architecture is applicable for larger operands. It also uses two different structures of sum generators which compute the added result of the operands by incorporating the complement of the carriers. It is designed and simulated using Xilinx ISE 13.2 and it is coded in Verilog HDL. The performance of the proposed HBK-MSG adder is analyzed by measuring area, delay and power consumption. The proposed 64-bit HBK MSG adder reduces the energy consumption by 62.98%, 48.05%, 33.09%, 28.12% and delay by 63.54%, 48.46%, 34.58%, 28.15% when compared with the existing adder designs such as RCA, CSLA, PPF/CSSA_4 and hybrid adder.
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