Abstract
Area, Power and Delay optimizations are the challenges in current digital IC design. Processors which are being currently used require adder units. In this work, different type of 32-bit VLSI adders will be studied and their design implementation will be done. Some of the adders were designed using 3-2 compressor. Some of the 32-bit hybrid adders is proposed by using differing types of combination of adders and logic. The combination includes parallel prefix adders like Kogge-Stone adder (KSA), Brent-Kung adder (BKA), Ladner-Fischer adder (LFA) and Han-Carlson adder (HCA). Two 64-bit hybrid adders is designed by analyzing the performance of the 32-bit designed hybrid adders and by selecting the best 32-bit adders. Analysis of the adder performance can be done in terms of Area (Number of LUT s), Delay (nS) and Power (W) analysis is performed with the help of Xilinx ISE 14.7, a Verilog synthesis software and implementation of the same using Verilog HDL family Spartan-6 selecting device XC6SLX16 choosing grade speed -3.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.