Cost analysis study of variable parallel prefix adders using altera cyclone IV FPGA kit

Abstract

Two operands addition is an essential unit in many embedded and digital signal processors as it is considered as the basic building block for other arithmetic operations. However, as one of the processor's performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. Thus, efficient adder design and implementation attracted many digital arithmetic designers especially those implemented for reconfigurable hardware such as Field Programmable Gate Array (FPGA) design. In this paper, we provide efficient FPGA implementations of five parallel prefix adders namely: Kogge-Stone Adder (KSA), Brent-Kung Adder (BKA), Han-Carlson Adder (HCA), Sklansky Adder (SkA), and Ladner-Fischer Adder (LFA) using Altera Cyclone IV as a target FPGA device. As a result, the comparison between different adders shows that KSA recorded the best values of critical path delay with 4.504 ns for 64 bits while BKA recorded the least design area results with 223 logic elements for the same bit length. Finally, the comparison with previous designs illustrates that the proposed adders' implementations have enhanced the performance over many state- of-the-art designs with even more than 200%.