Performance Analysis of Parallel Prefix Adder for Datapath Vlsi Design

Abstract

All modern processor, including microprocessor, digital signal processor contain Arithmetic Logic Unit (ALU). The computing efficiency of these modern processor mainly depended on efficiency of ALU. An adder is the basic building block for an ALU which performs arithmetic as well as logic operations. The existing adders like half adder, full adder, ripple carry adder, carry skip adder and carry lookahead adders cannot meet the expected optimization goals, so in this paper proposed four type of Parallel prefix adder (PPA) like Sklansky adder, Kogge-Stone adder, Brent-Kung adder and Ladner-Fischer adder. Parallel prefix adder [PPA] are kind of adder that uses prefix operation in order to do efficient addition. These adders are suited for binary addition with wide word. The Parallel prefix adders are derived from the carry look ahead adder. The performance analysis of PPA considered on area, delay and power consumption and simulation are carried out for 8 bit input data width.