Design and Study of Dadda Multiplier by using 4:2 Compressors and Parallel Prefix Adders for VLSI Circuit Designs

Abstract

In this paper, a new Dadda Multiplier is designed using 4:2 compressors and parallel prefix adders. From study and analysis in the literature reported in the recent past it is well known that a significant functional component in any processing module is a multiplier. In the processor, the multiplier takes up the majority of the hardware consumed as compared to any other arithmetic operations. Among the existing multiplication methods, Dadda multiplication method is advantageous in terms of reduction in delay.The main aim of a quality multiplier is to be as fast and consume as low area as possible. To decrease the delay of Dadda multiplier we have employed 4:2 compressor in the reduction stage. In the proposed system, parallel prefix adders are used to add the final stage of the partial product. In this paper, 4 Dadda multipliers employing 4:2 compressor block are proposed using Sklansky adder (SA), Kogge-Stone adder (KSA), Brent-Kung adder (BKA), and Ladner-Fischer adder (LFA). The proposed multiplier designs and conventional design are simulated on Xilinx Vivado 201S.2. The proposed designs are analyzed concerning conventional multiplier structure in terms of parameters delay (ns) and area (No. of LUTs).