An Efficient Quasi Comparison-free Bidirectional Architecture for Sorting Algorithm

Abstract

A novel low-power, high-speed quasi-comparison free bidirectional architecture for sorting algorithm is proposed in this paper. In bidirectional sorting, the set of data to be sorted is divided into low index and high index parts. Bidirectional sorting enables the tasks to be done in the higher and lower index parts simultaneously. The proposed architecture improves the performance of the bidirectional architecture by reducing power and area consumption. Along with power and area reduction, the delay has also been significantly lowered. With the modifications in the modules of bidirectional architecture, there is no need to switch from count to selection mode, which leads to a lot of power consumption in the overall architecture. The proposed bidirectional architecture is coded in Verilog HDL using Xilinx ISE and Cadence Genus synthesis solution with 45nm technology is used to synthesize the architecture. The performance of proposed architecture is compared with the existing architecture concerning the number of required sorting cycles, power, area, and delay. The results show that at the expense of the same number of sorting cycles, power consumption, are, and delay are notably reduced by the proposed architecture. With the improvements achieved in the proposed bidirectional architecture, it is an efficient and economic sorting architecture for many applications.