Abstract
Error control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high number of errors to be corrected by any scheme used in NoC. The high correction capability with moderate number of check bits along with the reduction in power and area requires further investigation in the accuracy of the reliability model. In this paper, reliability analysis is performed by modeling the residual error probability Presidual which represents the probability of decoder error or failure. New model to estimate Presidual of MECCRLB is derived, validated against simulation, and compared to HPC to assess the capability of MECCRLB. The results show that HPC outperforms MECCRLB from reliability perspective. The former corrects all single and double errors, and fails in 5.18% cases of the triple errors, whereas the latter is found to correct all single errors but fails in 32.5% of double errors and 38.97% of triple errors.
Highlights
On-chip communication between the many components integrated on a single chip is facing many reliability issues along with the stringent area and power constraints
Another optimization made In Joint Crosstalk Aware Multiple Error Correction (JMEC) to correct adjacent errors the used of changed interleaving distance between adjacent bits makes the correction of nine adjacent errors possible (Gul and Chouikha,2017) Duplication with two dimensional parities was proposed to provide up to seven errors detection (Flayyih and Samsudin,2014) or six errors detection and single error correction
RELIABILITY ANALYSIS Reliability can be measured by calculating the residual error probability (Presidual), which represents the probability of decoder error or failure; this is a complement to the probability of proper decoding which is the sum of the probabilities of correcting random errors and burst errors
Summary
On-chip communication between the many components integrated on a single chip is facing many reliability issues along with the stringent area and power constraints. The authors show huge reduction in area and power consumption as compared to(Fu ,2009) They show that their method can correct burst errors of four bits or random error of eleven bits which resulted in lower probability of residual error rate which means higher reliability. The high error correction capability of MECCRLB with low number of parity bits required along with the reduced circuit complexity motivates the requirement of further analysis of this scheme to verify its higher reliability level compared to HPC. This is supported by the fact that correction capability is upper limited by the Hamming distance emerging from the data redundancy.
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