Parallel Plane Breakdown Voltage Research Articles

Hybrid Edge Termination in Vertical GaN: Approximating Beveled Edge Termination via Discrete Implantations

This work examines a new hybrid edge termination structure for vertical GaN diodes. The hybrid JTE-GR termination consists of superimposed guard rings (GRs) onto a junction termination extension (JTE), resulting in zones with alternating implantation depths. The charge profile of the hybrid termination is developed by integrating the charge in the termination region across its length. An optimization strategy for designing the geometry is proposed by fitting the charge profile in the termination to that of a negative bevel edge reference termination. As the number of rings ranges from 4 to 12, it is shown via simulation that the optimized hybrid structure exhibits breakdown voltages between 92% and 95% of the ideal parallel plane breakdown voltage. Despite having similar breakdown voltages, by increasing the number of rings, the charge profile of the reference bevel termination is more closely fit. This results in a better approximation of the breakdown voltage response to variations in the p-layer doping concentration and thickness. The proposed design methodology and structure allow the design of high-voltage device termination geometry with minimal computationally expensive TCAD optimization.

Simulation of gradient floating field limiting rings for 4H-SiC power devices

In order to have higher breakdown voltage (BV) for 4H-SiC power devices, a novel edge termination structure with gradient floating field limiting rings (FFLR) is proposed. The device blocking performance between conventional FFLR and proposed structures are compared by 2-D numerical device simulation. The BV can be increased by 10% and 20% of parallel plane breakdown voltage with the same P-well and epitaxial parameters when step is 0.2μm and 0.4μm.

Design of selective-area growth compatible fully-vertical GaN p-i-n diodes with dielectric vertical sidewall appended edge termination schemes

While a slew of edge termination schemes for gallium nitride (GaN) power devices have been proposed and experimentally demonstrated to date, all of them suffer from the inability to achieve breakdown voltage close to ideal parallel-plane breakdown voltage. Further, they are exclusively processed using implantation or dry etching based methods, both of which are known to introduce additional defects and lattice damage leading to large leakage components. In this work, we develop and design novel dielectric vertical sidewall appended edge termination (DiVSET) schemes that are surface-charge resilient and capable of achieving ideal parallel-plane breakdown voltage. These edge termination schemes are compatible with plasma-assisted molecular-beam epitaxy facilitated silicon nitride shadowed selective-area growth (SNS-SAG) processing protocol, recently developed by us. The SNS-SAG protocol is uniquely capable of processing smooth, lattice damage-free GaN interfaces and vertical sidewalls that can reduce the leakage current by several orders of magnitude compared to conventional implant and dry etching based GaN processing. Together with the SNS-SAG processing, the DiVSET schemes offer an enabling technology for high-performance ultra-low leakage GaN power devices.

Characteristic and Robustness of Trench Floating Limiting Rings for 4H-SiC Junction Barrier Schottky Rectifiers

In this letter, planar floating limiting rings (FLRs) and trench FLRs with different trench depths for the 4H-SiC junction barrier Schottky (JBS) rectifiers are analyzed and compared with simulations and experiments. Compared with the planar FLRs, the experimental results present that the first ring spacing window that termination efficiency exceeds 80% of the parallel plane breakdown voltage (BV) can be widened and termination area can be reduced at the same BV by adopting the trench FLRs. The simulations also indicate that there is an optimal trench depth for the trench FLRs and a smaller sidewall angle can achieve better device performance. Additionally, the repetitive avalanche current stress measurements imply that the trench FLRs has better robustness regarding the BV shift, achieving better device reliability.

Theoretical and Experimental Study of 13.4 kV/55 A SiC PiN Diodes with an Improved Trade-Off between Blocking Voltage and Differential On-Resistance.

In this paper, a 13.4 kV/55 A 4H-silicon carbide (SiC) PiN diode with a better trade-off between blocking voltage, differential on-resistance, and technological process complexity has been successfully developed. A multiple zone gradient modulation field limiting ring (MGM-FLR) for extremely high-power handling applications was applied and investigated. The reverse blocking voltage of 13.4 kV, close to 95% of the theoretical value of parallel plane breakdown voltage, was obtained at a leakage current of 10 μA for a 100 μm thick, lightly doped, 5 × 1014 cm−3 n-type SiC epitaxial layer. Meanwhile, a fairly low differential on-resistance of 2.5 mΩ·cm2 at 55 A forward current (4.1 mΩ·cm2 at a current density of 100 A/cm2) was calculated for the fabricated SiC PiN with 0.1 cm2 active area. The highest Baliga’s figure-of-merit (BFOM) of 72 GW/cm2 was obtained for the fabricated SiC PiN diode. Additionally, the dependence of the breakdown voltage on transition region width, number of rings in each zone, as well as the junction-to-ring spacing of SiC PiN diodes is also discussed. Our findings indicate that this proposed device structure is one potential candidate for an ultra-high voltage power system, and it represents an option to maximize power density and reduce system complexity.

Numerical simulation of p-type diamond Schottky barrier diodes for high breakdown voltage

P-type diamond devices have high potential for power semiconductors due to their high critical field, hole mobility, and thermal conductivity. The electrical characteristics of p-type pseudovertical diamond Schottky barrier diodes (SBDs) were investigated by numerical simulation. The impact ionization coefficients were required to obtain the breakdown voltage. They were revised to satisfy a parallel-plane breakdown field of 10 MV/cm. The doping concentration and thickness of a low-doped drift layer were key parameters in determining the parallel-plane breakdown voltage. The p-type pseudovertical diamond SBDs exhibited lower breakdown voltage than the parallel-plane breakdown voltage because field crowding occurred at the edge of the cathode. When the doping concentration and thickness of the p− drift layer were 1016 cm−3 and 4 µm, respectively, the breakdown voltage of the p-type pseudovertical diamond SBD was 961 V, which was considerably less than the parallel-plane breakdown voltage of 3646 V.

A Comparative Study 4500-V Edge Termination Techniques for SiC Devices

This paper compares five edge termination techniques for SiC high-voltage devices: single zone junction termination extension (JTE), ring assisted-JTE (RA-JTE), multiple floating zone-JTE, hybrid-JTE, and floating field rings. PiN diodes with these edge terminations were fabricated on a 4.5kV-rated 4H-silicon carbide (4H-SiC) epi-layer. It was experimentally demonstrated that the Hybrid-JTE provides a nearly ideal breakdown voltage (~ 99% of the ideal parallel plane breakdown voltage) with a stable avalanche blocking behavior. RA-JTE, with tight control of the JTE implant dose, is demonstrated to be the most area-efficient edge termination structure for SiC power devices.

Design and experiment of 4H-SiC JBS diodes achieving a near-theoretical breakdown voltage with non-uniform floating limiting rings terminal

In this paper, a 4H-SiC Junction Barrier Schottky diode (JBS) with non-uniform floating limiting rings (FLRs) has been investigated and fabricated using n type 4H-SiC epitaxial layer with thickness of 31μm and doping concentration of 3.3×1015cm−3. According to the simulated results, the key parameters of a FLRs design to achieve a high voltage are the minimum space between two adjacent doped rings, spacing growth step and number of rings. The experimental results also show a great agreement with simulated results. Meanwhile, a near-ideal breakdown voltage of 3.7kV was achieved, which yield around 95% of the parallel-plane breakdown voltage. The forward characteristics show that the fabricated JBS diodes have a forward current density of 210A/cm2 at 3V and a specific on-resistance (Rsp-on) of 7.58mΩcm2. Different FLRs parameters have no effect on the forward device performance.

Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications

Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT2 technique increases the breakdown voltage (VBR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT2 used for a 3 kV 4H-SiC bipolar vertical diode is presented. Simulations using TCAD SENTAURUS software show that a maximum breakdown voltage of 3286 V at room temperature can be achieved with a deep trench of 20μm corresponding to 98 % of a parallel plane breakdown voltage for the drift layer of 18 μm. Those simulations also point out the important impact of the structure of the trench; the dielectric critical electric filled (Ec), the permittivity (εr) of the dielectric filled, etching defects as microtrench, fixed charges at the interfaces...on the VBR of power device.

Robust Trench Buried-Guard-Ring-Based Termination for Charge Balanced Devices

A major limitation on the performance of high-voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The proposed termination scheme was applied toward a 1350-V fast recovery diode and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after high-temperature reverse bias testing due to mobile ion contamination from packaging mold compound.

Trench Multiple Floating Limiting Rings Termination for 4H-SiC High-Voltage Devices

A junction termination method adopting heavily doped p-well rings with a shallow trench for each ring, named as a trench multiple floating limiting rings (TMFLRs), is analyzed and fabricated without any additional process in 4H-SiC junction barrier Schottky diode. A breakdown voltage of 6.7 kV is achieved using TMFLRs structure on an epitaxial layer with thickness of 50 $\mu \text{m}$ , while the breakdown voltage of the conventional planar FLRs structure with the same termination area is only 5.7 kV. The experimental result has demonstrated that the TMFLRs termination structure yields about 90% of the parallel plane breakdown voltage. In addition, the simulation results show that the TMFLRs make the bulk peak electric field ( $E_{p,\text {bulk}})$ reduce and move away from the device surface, successfully making the interface peak electric field ( $E_{p,\text {interface}})$ decrease by about 30% compared with a conventional planar FLRs structure when same reverse voltages applied.

Design, fabrication and characterization of mesa combined with JTE termination for high-voltage 4H–SiC PiN diodes

Mesa combined with JTE termination structures for high-voltage 4H–SiC PiN diodes are designed, fabricated, and characterized in this paper. Designs based on simulation are performed to investigate the influence of the mesa shape on breakdown for SiC PiN diodes. It is found that a deeper mesa height and a smaller mesa angle contribute to a higher breakdown voltage owing to a smoother and more uniform surface electric field distribution. A maximum reverse blocking voltage of 3.8 kV and an on-state voltage drop of 3.4 V at 100 A/cm2 are obtained from the fabricated diodes with a mesa height of 2.1 μm and a mesa angle of 22°, corresponding to about 80% of a parallel plane breakdown voltage for the drift layer with a thickness of 30 μm. Additionally, the dependence of the breakdown voltage on the JTE length observed in the fabricated diodes shows a good agreement with the simulated results in the trend.

Improved Planar MOS Barrier Schottky (PMBS) Rectifier with High-<i>k</i> Dielectrics

In this paper, an improved planar MOS barrier Schottky (PMBS) rectifier is proposed which utilizes the PECVD deposited high-k semi-insulating polycrystalline silicon (SIPOS) as the MOS area gate dielectrics for the first time. By adopting the high-k SIPOS as the MOS gate dielectrics, the peak electric field at the interface betwwen dielectrics layer and SiC can be significantly relieved and the device reliability can obviously enhanced without considerable degradation of on-state characteristics. With the optimized the thickness of the SIPOS film, the breakdown voltage (BV) of 1500V for the fabricated device was achieved, which is approximately corresponds to 85% of the theoretical parallel plane breakdown voltage value calculated from the used epilayer structure. And the specific on-state resistance (RSP-ON) is about 4.2mΩ•cm2. The corresponding figure-of-merit of VB2/ RSP-ON for the proposed device is 535.7MW/cm2.

Robust Double-Ring Junction Termination Extension Design for High Voltage Power Semiconductor Devices Based on 4H-SiC

In this study, a new robust double-ring junction-termination-extension (DR-JTE) for high-voltage pn-diodes is presented and analyzed using numerical simulations. As figured out, the DR-JTE reduces the electrical field at both, the edge of the single-JTE region and the MESA-transition, respectively. Thereby, due to the reduction of the electrical field, the maximum breakdown voltage is increased to 91.5% of the theoretical, parallel-plane breakdown voltage of 6.5kVand the maximum acceptable deviation of the optimum implantations dose is twice than that of the single-JTE structure. Furthermore, due to the internal ring, the MESA-transition is shielded from the electrical field and therefore the breakdown voltage is much less affected by the angle of the MESA.

An Improved ICP Etching for Mesa-Terminated 4H-SiC p-i-n Diodes

An improved Bosch etching process using inductively coupled plasma system has been investigated for the etching of 4H-silicon carbide (SiC). By optimizing the etch parameters, a mesa structure with nearly vertical sidewall and without microtrench at the bottom corner has been fabricated, and the formation and elimination of the microtrench are preliminarily discussed for the Bosch cycles in this paper. Scanning electron microscopic analysis was used to demonstrate the etched morphology under different etching conditions. Simple mesa-terminated 4H-SiC p-i-n diodes were fabricated. The effect of the improved mesa structure on the dc characteristics of the diodes has been experimentally verified by comparing with the nonoptimized mesa structure with microtrench. The results exhibited a completely consistent forward tendency and a similar reverse leakage level less than −900 V for both diodes, but different blocking performances. A maximum blocking voltage of 1565 V at room temperature was obtained from the nonmicrotrenched device with a mesa height of 4.3 $\mu \text{m}$ , corresponding to 66% of a parallel plane breakdown voltage for the drift layer of 15 $\mu \text{m}$ . Slight microtrench is the main cause of premature breakdown.

4H-SiC Diode Avalanche Breakdown Voltage Estimation by Simulation and Junction Termination Extension Analysis

This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (>15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

Designing and Fabrication of the VLD Edge Termination for 3.3 kV SiC SBD

Edge termination guaranteeing high breakdown voltage and robustness in its fabrication are required in SiC power devices. We newly employed the VLD edge termination for 3.3 kV-rated SiC SBDs, which was formed by Al ion implantation using a resist mask having a varying thickness. The breakdown voltage is recorded to be over 96% of the parallel-plane breakdown voltage, and the reverse bias characteristics are well accorded with the result of TCAD simulation.

Breakdown Characteristics of 15-kV-Class 4H-SiC PiN Diodes With Various Junction Termination Structures

15-kV-class 4H-SiC PiN diodes with various junction termination structures have been experimentally investigated. Employment of the space-modulated junction termination extension (SM-JTE) and the two-zone JTE have realized a breakdown voltage over 15 kV, corresponding to 93% of the parallel-plane breakdown voltage. The window of the implanted JTE dose to achieve the ultrahigh voltage has been enlarged, which indicates the robustness to the deviation of effective JTE dose. From the comparison of the experimental JTE-dose dependence of breakdown voltage with the numerical device simulation, a shift toward the heavier JTE-dose region was observed. To explain the phenomenon, effects of the charges at the SiO2/SiC interface are discussed.

Experimental Study on Various Junction Termination Structures Applied to 15 kV 4H-SiC PiN Diodes

Breakdown characteristics of 4H-SiC PiN diodes with various JTE structures have been investigated. By combining two-zone JTE and Space-Modulated JTE (SM-JTE), a breakdown voltage over 15 kV, corresponding to about 93 % of the parallel-plane breakdown voltage, was realized. The window of optimum JTE dose to obtain high breakdown voltage was widened, which indicates the robustness to the deviation of JTE dose. By comparing the breakdown voltage obtained by simulation and experimental results, impacts of the charge near the SiO2/SiC interface are discussed.