Abstract
In this paper, an improved planar MOS barrier Schottky (PMBS) rectifier is proposed which utilizes the PECVD deposited high-k semi-insulating polycrystalline silicon (SIPOS) as the MOS area gate dielectrics for the first time. By adopting the high-k SIPOS as the MOS gate dielectrics, the peak electric field at the interface betwwen dielectrics layer and SiC can be significantly relieved and the device reliability can obviously enhanced without considerable degradation of on-state characteristics. With the optimized the thickness of the SIPOS film, the breakdown voltage (BV) of 1500V for the fabricated device was achieved, which is approximately corresponds to 85% of the theoretical parallel plane breakdown voltage value calculated from the used epilayer structure. And the specific on-state resistance (RSP-ON) is about 4.2mΩ•cm2. The corresponding figure-of-merit of VB2/ RSP-ON for the proposed device is 535.7MW/cm2.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
