Analog Multiplier Research Articles

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

Determination of the Boltzmann constant by the equipartition theorem for capacitors

A new experimental set-up for measurement of the Boltzmann constant is described. The statistically averaged square of voltage is measured for different capacitances C. The Boltzmann constant is determined by the equipartition theorem . For fixed capacitance, voltages could be measured for different temperatures. The set-up consists of low-noise, high-frequency operational amplifiers ADA4898-2. An instrumental amplifier is followed by an inverting amplifier, the square of the voltage is created by an analog multiplier AD633, and finally, the averaged signal is measured by a multimeter. More than ten high-school students were able to measure the Boltzmann constant with the experimental set-up in the 5th Experimental Physics Olympiad with excellent accuracy compared to the price, conditions and available time for the experiment. A new derivation of the important statistical physics theorems by Nyquist and Callen–Welton is given in an appendix at the level of introductory courses in physics studied by future teachers. To understand the work of the experimental set-up, it is only necessary to know the equipartition theorem.

A new strategy to design low power translinear based CMOS analog multiplier

This paper deals with a new method to design CMOS analog multiplier which operates in four quadrants. The main core of the proposed multiplier circuit consists of two common pairs of translinear loops which make a symmetrical configuration for the multiplier circuit. This property minimizes the error, because the resulted error in two squarer circuits are subtracted from each other, then the precision is increased. Also, the shared bias branch in the multiplier circuit causes to consume low power in comparison with conventional structures. In other word, both of the squarer circuits use single bias branch instead of two. The post layout of the circuit is designed and simulated using Cadence and HSPICE software, with TSMC and level 49 parameters (BSIM3v3) in 180 nm technology. The simulation results demonstrate a linearity error of 0.69%, a THD of 0.97% in 1 MHz, a -3dB bandwidth of 623 MHz and a maximum power consumption of 92.34 μW.

The Transfer Function of Amplitude Modulation Circuits Using Varactor Diode

Amplitude modulation (AM) is widely used for not only wireless communications but also sensing and monitoring biomaterials as well as scientific data. Recently analog multipliers are attracting much attention to mitigate modulation distortion and insufficient dynamic range in the traditional way of AM. However, as the circuit of analog multiplier is complicated and contains many transistors, its use may encounter difficulty in IC implementation. Varactor diode is a capacitor of which capacitance varies according to the change of reverse bias voltage and has advantages of small size (easily integrated), high speed operation, low thermal noise, and low power consumption. Based on this property, varactor diode can work as multiplier so that it can be employed for AM in place of analog multiplier. This brief presents AM circuit using varactor diode of simple structure and shows for the first time a theoretical way to determine its transfer function. Theoretical analysis is validated by using hardware simulation on an example circuit.

Voltage Differencing Buffered Amplifier based Voltage Mode Four Quadrant Analog Multiplier and its Applications

In this paper a voltage mode four quadrant analog multiplier (FQAM) using voltage differencing buffered amplifier (VDBA) based on quarter square algebraic identity is presented. In the proposed FQAM the passive resistor can be implemented using MOSFETs operating in saturationregion thereby making it suitable for integration. The effect of non idealities of VDBA has also been analyzed in this paper. Theoretical propositions are verified through SPICE simulations at 0.18μm CMOS technology node and the simulation results are found in close agreement with theoretical values. The supply voltage is taken as ± 1V and the value of the bias current is set to 40µA.The simulated total harmonic distortion (THD) is observed to be under 3% and the total power dissipation is found as 627µW. The workability of the proposed FQAM is also tested through two applications, namely, an amplitude modulator and a rectifier. The simulated results corroborate the theoretical propositions.

Analog Multiplier Based on Squarer Cells

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are proposed with the parity-preserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’s algorithm and its enhanced version called the K-algorithm, utilizing the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be utilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed multipliers are much better than the existing designs regarding the main criterions used in reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.

A New Floating Memristor Based on CBTA with Grounded Capacitors

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors.

Long Short-Term Memory Network Design for Analog Computing

We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

An Improved Time-Division Analog Multiplier

ABSTRACTAn improved version of the analog multiplier recently appeared is presented. This uses less number of components, hence less complex and economical, and has better accuracy.

Complex Dynamics of the Chua’s Circuit System with Adjustable Symmetry and Nonlinearity: Multistability and Simple Circuit Realization

Background: Since the invention of Chua’s circuit, numerous generalizations based on substitution of the nonlinear function have been reported. One of the generalizations is obtained by replacing the piecewise-linear with the cubic and/or quadratic polynomial. These nonlinearities are used to be implement using analog multipliers which are relatively expensive. In this realization we propose a different approach to synthetize both cubic and quadratic nonlinearities of empirical Chua’s circuit. Methods: The idea is to use diodes, Opamps and resistors to derive a PWL approximation of the cubic and quadratic functions. To demonstrate some complex phenomena observed in the system using the fourth order Runge-Kutta numerical integration method with a very small integration step. The bifurcation diagram which is the plot of local maxima of the temporal trace of a system’s coordinate as a function of the control parameter also constitutes an excellent tool for the study of dynamic systems. Results: The above mentioned standard nonlinear analysis tools have been exploited and it is found that the system with adjustable symmetry experiences a plethora of symmetric and asymmetric coexisting attractors. A particular feature of the system is related to the simplicity of the corresponding electronic analog circuit (no analog multiplier chip used to implement the cubic and quadratic nonlinearities). Conclusions: It is observed that the proposed Chua’s circuit system is more flexible (both symmetric and asymmetric) and displays complex dynamics behaviors of symmetric and asymmetric coexisting attractors. Note that this striking dynamic can be exploited in encryption algorithms.

Fully Integrated Memristor and Its Application on the Scroll‐Controllable Hyperchaotic System

In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll‐controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor‐based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor‐based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor‐based hyperchaotic system are verified with the GlobalFoundries’ 0.18 μm CMOS process using Cadence IC Design Tools. The postlayout simulation results demonstrate that the memristor‐based fully integrated hyperchaotic system consumes 90.5 mW from ±2.5 V supply voltage and it takes a compact chip area of 1.8 mm2.

Antimonotonicity, chaos, quasi-periodicity and coexistence of hidden attractors in a new simple 4-D chaotic system with hyperbolic cosine nonlinearity

Recently, the study of systems with hidden attractors has become one of the most followed topics owing to their fundamental and technological importance. This contribution is focused on a new simple 4-D chaotic system (whose nonlinearity is a hyperbolic function) inspired by the quadratic system introduced by [Jay and Roy Nonlinear Dyn (2017) 89:1845–1862]. Basic properties of the new system are discussed and its complex behaviors are characterized using dynamic systems analysis tools. This system exhibits a rich repertoire of dynamic behaviors including chaos, chaos 2-torus, and quasi-periodic. Other interesting phenomena such as multistability, antimonotonicity, and torus-doubling bifurcations are also reported. Moreover, the hyperbolic cosine nonlinearity is easily implemented by using a pair of semiconductor diodes (no analog multiplier is involved). We confirm the feasibility of the proposed theoretical model using PSpice simulations and a physical realization based on an electronic analog implementation of the model.

High-Speed Remote Power Measurement by Communication of the Maximum and Minimum Measurement Value

A typical digital power measurement device samples voltage and current several times for one period of voltage and current to determine the root mean square. It is the typical way that the phase begins counting at the voltage zero point and the corresponding power is determined by the value of the counter at the current zero point. The digital power measurement in the above structure reduces sensing precision because, as the frequency of the subjects increases, the number of measurement decreases in one period. In particular, if the frequency to be measured is similar to the sampling frequency, it is practically impossible to measure the power. Therefore, in this paper, I propose a new power measurement system that can detect the maximum and minimum values of instantaneous power and then measure the power using the values. In the proposed method, the relationship between the maximum and minimum values of instantaneous power, apparent power and effective power is investigated and the apparent power and the effective power are identified using the instantaneous power maximum and minimum difference and sum. In the proposed power measurement technique, the measured power–frequency limit is independent of the sampling frequency of the digital part, and is determined by the performance of the analog multiplier and the maximum minimum detection circuit. It is advantageous that the proposed method can measure the accurate power irrespective of the frequency of the subjects to be measured. The validity of the proposed method is demonstrated by simulation and experiment.

Low power binomial coefficient architecture for unused spectrum detector

Recently, low power architecture is the major requirement in wireless devices. Cognitive radio is the most significant technology to realize the problem of choosing the temporarily unused channels (Sarijari et al. in EURASIP J Wireless Commun Netw 2015:221, 2015). In this paper, the binomial coefficient (nCk) architecture is proposed for finding the possibilities of detecting the unused spectrum in the cognitive radio network. A novel factorial algorithm is designed using a modified parallel multiplier with Vedic multiplication method (Maharaja in Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2001). Compared to existing factorial algorithm (Saha et al. in Microelectron J 42:1343–1352, 2011), the proposed novel factorial algorithm can perform low power, high speed and occupy less number of logic elements because of the simple data-path reduction method using decoder circuit. A new binomial coefficient architecture is designed using the proposed factorial algorithm. The proposed modules are designed and implemented in Altera Cyclone II FPGA family.

Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of $$\pm \,v_x \pm \,v_y$$ are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1 $$\%$$ for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 $$\upmu $$ W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 $$\upmu $$ m CMOS standard technology is used, showing a silicon area consumption of $$280\,\upmu \hbox {m} \times 400\,\upmu $$ m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.

Design of Radix-8 Mbe-Multiplier Based on Efficient Parallel Multiplier Accumulator

Design of Radix-8 Mbe-Multiplier Based on Efficient Parallel Multiplier Accumulator

Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant analog multiplier

This paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit.

Analog Multiplication in Random Demodulation Analog–to–Information Converters

Aim of this paper is to compare in Analog-to-Information Converters the working principles of the two devices typically used to perform the operation of multiplication: mixers and analog multipliers. The comparison has been experimentally realized on two AIC prototypes based on the Random Demodulation principle: the former employing a mixer, the latter employing an analog multiplier.

A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier

In this paper, a novel current mode enhanced input range four-quadrant analog multiplier is presented. The proposed class AB based translinear current squarer allows the designer to control the input range via a digital code. Moreover, the proposed scheme improves the linearity of the circuit and has a high robustness against process variations. The Post-layout and Monte Carlo simulations of the multiplier in a 0.18 μm standard CMOS technology show an input range of (1+m) × 10 μA (where ‘m’ is an adjustable parameter), a THD of 1% (@1 MHz), a −3 dB bandwidth of 332.3 MHz (for m = 3) and a power consumption of 186 μW.