Low power binomial coefficient architecture for unused spectrum detector

Abstract

Recently, low power architecture is the major requirement in wireless devices. Cognitive radio is the most significant technology to realize the problem of choosing the temporarily unused channels (Sarijari et al. in EURASIP J Wireless Commun Netw 2015:221, 2015). In this paper, the binomial coefficient (nCk) architecture is proposed for finding the possibilities of detecting the unused spectrum in the cognitive radio network. A novel factorial algorithm is designed using a modified parallel multiplier with Vedic multiplication method (Maharaja in Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2001). Compared to existing factorial algorithm (Saha et al. in Microelectron J 42:1343–1352, 2011), the proposed novel factorial algorithm can perform low power, high speed and occupy less number of logic elements because of the simple data-path reduction method using decoder circuit. A new binomial coefficient architecture is designed using the proposed factorial algorithm. The proposed modules are designed and implemented in Altera Cyclone II FPGA family.