A new strategy to design low power translinear based CMOS analog multiplier

Abstract

This paper deals with a new method to design CMOS analog multiplier which operates in four quadrants. The main core of the proposed multiplier circuit consists of two common pairs of translinear loops which make a symmetrical configuration for the multiplier circuit. This property minimizes the error, because the resulted error in two squarer circuits are subtracted from each other, then the precision is increased. Also, the shared bias branch in the multiplier circuit causes to consume low power in comparison with conventional structures. In other word, both of the squarer circuits use single bias branch instead of two. The post layout of the circuit is designed and simulated using Cadence and HSPICE software, with TSMC and level 49 parameters (BSIM3v3) in 180 nm technology. The simulation results demonstrate a linearity error of 0.69%, a THD of 0.97% in 1 MHz, a -3dB bandwidth of 623 MHz and a maximum power consumption of 92.34 μW.