Parallel Decoder Architecture Research Articles

A Real-Time License Plate Detection and Recognition Model in Unconstrained Scenarios.

Accurate and fast recognition of vehicle license plates from natural scene images is a crucial and challenging task. Existing methods can recognize license plates in simple scenarios, but their performance degrades significantly in complex environments. A novel license plate detection and recognition model YOLOv5-PDLPR is proposed, which employs YOLOv5 target detection algorithm in the license plate detection part and uses the PDLPR algorithm proposed in this paper in the license plate recognition part. The PDLPR algorithm is mainly designed as follows: (1) A Multi-Head Attention mechanism is used to accurately recognize individual characters. (2) A global feature extractor network is designed to improve the completeness of the network for feature extraction. (3) The latest parallel decoder architecture is adopted to improve the inference efficiency. The experimental results show that the proposed algorithm has better accuracy and speed than the comparison algorithms, can achieve real-time recognition, and has high efficiency and robustness in complex scenes.

RS-LDPC stochastic joint decoding algorithm

Due to complexity issues, low-density parity-check (LDPC) codes often use a partial parallel decoding architecture, which cannot easily meet the requirements of high-speed and ultra-high-speed applications. Conversely, the Reed-Solomon (RS) codes often use hard decision decoding algorithms in existing decoding schemes. Therefore, there is room for further optimization in the complexity and performance of concatenated RS -LDPC decoding. In this paper, we propose an RS-LDPC stochastic joint iterative decoding algorithm based on the principle of stochastic computing. This algorithm inherits the advantages of the low complexity of stochastic LDPC decoders and the feature of stochastic RS decoding algorithms, which can use hard decoders. Meanwhile, the decoding performance is improved through the joint iterative decoding architecture. In this respect, we design a test-vector generation method based on LDPC probability values and adopt a novel additional extrinsic information generation mechanism. Such a mechanism is applied to the structure of the variable nodes of the stochastic LDPC decoder. The simulation results show that at a bit error rate of $10^{-6}$, the proposed algorithm can obtain a gain of 0.3 dB as compared with the RS-LDPC cascaded decoding scheme using floating-point belief propagation and Berlekamp -Massey hard decision decoding algorithm. Its implementation complexity is the complexity of a stochastic LDPC decoder and several RS hard decoders. The decoding latency is determined by the latency of the stochastic LDPC decoder. Therefore, the joint iterative decoding algorithm proposed in this paper has a very good application value.

Novel memory efficient LDPC decoders for beyond 5G

Beyond-5G wireless networks are expected to gain a excellent trade-off among computational accuracy, latency, and efficient use of available resources. This poses a significant challenge to the channel decoder. In this paper, a novel memory efficient algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity and hardware resources. The algorithm, called Check Node Self-Update (CNSU) algorithm, is based on layered normalized min-sum (LNMS) decoding algorithm while utilizing iteration parallel techniques to integrate both Variable Nodes (VNs) message and A-Posterior Probability(APP) message into the Check Nodes (CNs) message, which eliminates memories of both the VNs message and the APP message as well as updating module of APP message in CNs unit. Based on the proposed CNSU algorithm, design of partially parallel decoder architecture and serial simulations followed by implementation on the Stratix II EP2S180 FPGA are presented. The results show that the proposed algorithm and implementation bring a significant gain in efficient using of available resources, include reducing hardware memory resources and chip area while keeping the benefit of bit-error-rate (BER) performance and speeding up of convergence with LNMS, which are beneficial to apply in Beyond-5G wireless networks.

Efficient Parallel Decoding Architecture for Cluster Erasure Correcting 2-D LDPC Codes for 2-D Data Storage

Native 2-D low-density parity-check (LDPC) codes provide 2-D burst erasure correction capability and have promising applications in two-dimensional magnetic recording (TDMR) technology. Though carefully constructed rastered 1-D LDPC codes can provide 2-D burst erasure correction, they are not as efficient as 2-D native codes constructed for handling the 2-D span of burst erasures. Our contributions are twofold. First, we propose a new 2-D LDPC code with girth greater than 4 by generating a parity-check tensor through stacking permutation tensors of size $p\times p\times p$ along with the $i,j,k$ -axes. The permutations are achieved through circular shifts on an identity tensor along different coordinate axes in such a way that it provides a burst erasure correction capability of at least $p\times p$ . Second, we propose a fast, efficient, and scalable hardware architecture for a parallel 2-D LDPC decoder based on the proposed code construction for data storage applications. Through efficient indexing of the received messages in an RAM, we propose novel routing mechanisms for messages between the check nodes and variable nodes through a set of two barrel shifters, producing shifts along two axes. Through simulations, we show that the performance of the proposed 2-D LDPC codes matches a 1-D QC-LDPC code, with a sharp waterfall drop of three to four orders of magnitude over ~0.3 dB, for random errors over code sizes of ~32 kbits or equivalently ~ $180\times 180 2$ -D arrays. Furthermore, we prove that the proposed native 2-D LDPC codes outperform their 1-D counterparts in terms of 2-D cluster erasure correction ability. For $p=16$ and code arrays of size $48\times 48$ , we implemented the proposed design architecture on a Kintex-7 KC-705 field-programmable gate array (FPGA) kit, achieving a significantly high worst case throughput of 12.52 Gb/s at a clock frequency of 163 MHz.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates

Abstract. The wide range of code rates and code block sizes supported by todays wireless communication standards, together with the requirement for a throughput in the order of Gbps, necessitates sophisticated and highly parallel channel decoder architectures. Code rates specified in the LTE standard, which uses Turbo-Codes, range up to r=0.94 to maximize the information throughput by transmitting only a minimum amount of parity information, which negatively impacts the error correcting performance. This especially holds for highly parallel hardware architectures. Therefore, the error correcting performance must be traded-off against the degree of parallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on code block level to alleviate this trade-off. In this paper, we follow a cross-layer approach by combining system level knowledge about the rate-matching and the transport block structure in LTE with the bit-level technique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code decoder hardware architecture achieves coding gains of 0.4–1.8 dB compared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible hardware overhead and a resulting high area and energy efficiency and give post place and route synthesis numbers.

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.

Register Free Polar Codes Based Partially Parallel Encoder and Decoder Architecture

This paper presents about the partially parallel encoder and decoder architecture for polar-codes using register-free technique. In this paper, the folding transformation technique and register minimization technique are used for this architecture to reduce the circuit and timing complexity. In general, the polar codes are referred to a low complexity code to achieve the performance of channel carrying capacity in a binary-input memory-less channels. In the fully-parallel architecture, the hardware complexity is the major drawback which is high whereas in partially-parallel architecture the memory-sharing concept is utilized to overcome the complexity of hardware to attain the high throughput application. Thus, the temporary end results are saved within the registers instead of memories and multiplexers to manage the interlocking wires. Hence, the register aspect in polar code centered encoder and decoder architecture are eliminated. In an effort to support the information transmission efficiency stage, we get rid of the knowledge storage side (d-register) in stage-three and stage-four encoder and decoder method. Finally we reduce the 32 register elements for every data transmission process and mainly focus on the data storage and transmit function. Because the storage events are need to more time for data passing to one stage level to another stage.

LTE Turbo Decoding Parallel Architecture with Single Interleaver Implemented on FPGA

This paper describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP Long-Term Evolution standard. Considering the high data rates required by this standard, parallel decoding architecture is used. The parallel decoding latency is reduced N times compared with the serial decoding latency, N being the parallelization factor, usually a power of 2. The decoding performances are similar for both serial and parallel schemes, when very low decoding latency is added to this theoretical parallel latency value. Taking advantage of the quadratic permutation polynomial interleaver properties, and considering some specific FPGA block memory characteristics, a novel simplified parallel decoding scheme is proposed, including only one interleaver, independently of the N value. Moreover, for the single interleaver, we propose a solution that exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. In addition, an even-odd merge sorting network provides correct data to all N decoding units.

4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions

Two High Efficiency Video Coding (HEVC) extensions, namely, the scalable HEVC (SHVC) extension and multiview HEVC (MV-HEVC) extension, have been finalized in July 2014 by the Moving Picture Experts Group and Video Coding Experts Group. These two extensions enable additional features not covered in the first version of the HEVC standard such as spatial, fidelity, bitdepth, and color gamut scalability, as well as stereoscopic and multiview representations. In this paper, we propose a software parallel decoder architecture for the HEVC standard and its multilayer extensions, including SHVC and MV-HEVC extensions. The decoder consists of multiple instances of the OpenHEVC decoder, one instance to decode each layer with a communication between dependent layers to perform inter-layer predictions. The proposed multilayer HEVC decoder is parallel friendly and supports both wavefront parallelism to simultaneously process adjacent rows of the frame and frame-based parallelism to decode a set of temporal and spatial frames in parallel. Moreover, the most time-consuming operation introduced in the SHVC extension, namely, the resampling of the inter-layer reference picture in spatial scalability, is optimized in single instruction multiple data for x86 platform. We assess the complexity of the multilayer HEVC decoder with respect to the simulcast configuration. The multilayer decoder decoding two SHVC layers introduces in average 40%–71% additional complexity compared with the single layer HEVC decoder. Moreover, the low level optimizations with a hybrid parallel processing solution enable a real-time decoding of 4Kp60 enhancement layer on a 6-core Intel i7 processor running at 3.4 GHz.

FPGA implementation of low complexity LDPC iterative decoder

ABSTRACTLow-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm^2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.

High-Speed Architectures for Parallel BCH Decoders

Bose-Chaudhuri-Hocquenghen (BCH) error-correcting codes are now widely used in communication system and digital technology. The original iterative method is complex and time-consuming operations. An inversion less decoding method for binary BCH codes was proposed to simplify the Berlekamp-Massey algorithm, which can eliminate the bottleneck in long BCH decoder. For our considered parallel decoder architecture, the simplicity of this new method makes a simplified VLSI implementation possible.

Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA

Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.

Energy efficient low-cost video communications

Although traditional video coding is based on complex encoders and simple decoders, more recent codecs can reverse the complexity in order to provide low-cost encoders for mobile devices. However, the complexity is moved from the encoder to the decoder, accumulating high complexity on the decoder side. In this work, a parallel decoding architecture is proposed which exploits multiplecore processors to tackle this high complexity. In particular, the data distribution scheme in this architecture considers two parallelism levels: Group of Pictures and spatial frame distribution. Our results, for a four-core Multicore Processor, it is achieved a time reduction of up to 70% on average, with a negligible Rate-Distortion penalty. In addition, the usage of the CPU is also analyzed, reaching 80% on average and the energy consumption of the decoder is reduced up to 60%.

Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

High Throughput Parallel Fano Decoding

In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction in the code tree simultaneously. It is shown that the proposed BFA can achieve more than twice the decoding throughput compared to the conventional unidirectional Fano algorithm (UFA) and there is higher throughput improvement at low signal-to-noise ratio (SNR). This new BFA decoding technique is applied in the parallel convolutional decoding architecture in very high throughput systems, such as the WirelessHD system. Due to the variability in the decoding delays of the parallel codewords, a scheduler is introduced in the parallel Fano decoding architecture which can dynamically allocate the idle decoders to assist with decoding the other parallel codewords in a bidirectional manner. It is shown that the proposed parallel Fano decoding with scheduling can dramatically increase the decoding throughput compared to the parallel Fano decoding without scheduling, and its computational complexity is much lower than that of parallel Viterbi decoding, especially at high SNR. The performance of the parallel Fano decoding with different scheduling schemes is also compared and analyzed in detail in the paper.

A Parallel-Layered Belief-Propagation Decoder for Non-layered LDPC Codes

In this paper, we proposed a Parallel-Layered Belief-Propagation (PLBP) algorithm first, which makes a breakthrough in utilizing the layered decoding algorithm on the “non-layered” quasi-cyclic (QC) LDPC codes, whose column weights are higher than one within layers. Our proposed PLBP algorithm not only achieves a better error performance, but also requires almost 50% less iterations than the flooding algorithm. Then we propose a low-power partial parallel decoder architecture based on the PLBP algorithm. Our PLBP decoder architecture requires less area and energy efficiency than other existing decoders. As a case study, a multi-rate 9216-bit LDPC decoder is implemented in SMIC 0.13μm 1P6M CMOS technology. The decoder dissipates an average power of 87mW with 10 iterations at a clock frequency of 83.3 MHz. The chip core size is 7.59 mm 2 , and the die area occupies 10.82 mm 2 .

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.