Novel memory efficient LDPC decoders for beyond 5G

Abstract

Beyond-5G wireless networks are expected to gain a excellent trade-off among computational accuracy, latency, and efficient use of available resources. This poses a significant challenge to the channel decoder. In this paper, a novel memory efficient algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity and hardware resources. The algorithm, called Check Node Self-Update (CNSU) algorithm, is based on layered normalized min-sum (LNMS) decoding algorithm while utilizing iteration parallel techniques to integrate both Variable Nodes (VNs) message and A-Posterior Probability(APP) message into the Check Nodes (CNs) message, which eliminates memories of both the VNs message and the APP message as well as updating module of APP message in CNs unit. Based on the proposed CNSU algorithm, design of partially parallel decoder architecture and serial simulations followed by implementation on the Stratix II EP2S180 FPGA are presented. The results show that the proposed algorithm and implementation bring a significant gain in efficient using of available resources, include reducing hardware memory resources and chip area while keeping the benefit of bit-error-rate (BER) performance and speeding up of convergence with LNMS, which are beneficial to apply in Beyond-5G wireless networks.