Abstract
Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.
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