Register Free Polar Codes Based Partially Parallel Encoder and Decoder Architecture

Abstract

This paper presents about the partially parallel encoder and decoder architecture for polar-codes using register-free technique. In this paper, the folding transformation technique and register minimization technique are used for this architecture to reduce the circuit and timing complexity. In general, the polar codes are referred to a low complexity code to achieve the performance of channel carrying capacity in a binary-input memory-less channels. In the fully-parallel architecture, the hardware complexity is the major drawback which is high whereas in partially-parallel architecture the memory-sharing concept is utilized to overcome the complexity of hardware to attain the high throughput application. Thus, the temporary end results are saved within the registers instead of memories and multiplexers to manage the interlocking wires. Hence, the register aspect in polar code centered encoder and decoder architecture are eliminated. In an effort to support the information transmission efficiency stage, we get rid of the knowledge storage side (d-register) in stage-three and stage-four encoder and decoder method. Finally we reduce the 32 register elements for every data transmission process and mainly focus on the data storage and transmit function. Because the storage events are need to more time for data passing to one stage level to another stage.