Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications

Abstract

In this paper, we newly present a novel parallel polar decoding architecture that significantly reduces the processing latency for 5G wireless communications. Based on the original decoding tree, the proposed scheme first constructs the small trees that generate multiple soft-decision messages in parallel, potentially reducing the decoding latency compared to the previous serialized schemes. The hard-decision estimates are then calculated at the following merging step to decide the decoded outputs and to update the parallel trees. For each parallel tree, the parallel pruning scheme is newly utilized to further optimize the processing latency. In addition, we introduce an efficient parallel decoder architecture, successfully supporting the proposed low-latency algorithm. Implementation results show that the proposed 8-parallel polar decoder in 65nm CMOS uses only 267ns to decode a (1024, 512) polar codeword of 5G system, which is 1.67 times faster than the state-of-the-art design.