Parallel Decoding Research Articles

Fast Successive-Cancellation Decoding of Polar Codes: Identification and Decoding of New Nodes

The decoding latency of polar codes can be reduced by implementing fast parallel decoders in the last stages of decoding. In this letter, we present five such decoders corresponding to different frozen-bit sequences to improve the decoding speed of polar codes. Implementing them achieves significant latency reduction without tangibly altering the bit-error-rate performance of the code.

Parallel List Decoding of Convolutional Codes: Algorithm and Implementation

List decoding is a promising technique for machine type communications (MTC) and other applications that pursue the high-coding gain of convolutional codes. However, there are obstacles that degrade the availability of list decoding. In specific, non-tail-biting list decoding involves high demands of data storage, while tail-biting list decoding requires substantial computational resources to preserve the optimal performance. In this paper, we rethink the parallel list decoder design from the aspects of algorithm and implementation to circumvent the foregoing obstacles. On the one hand, internal relations among the multiple decoding sequences are revealed and leveraged to redesign the non-tail-biting list decoding algorithm, which enables the design to extricate from the massive storage expense. On the other hand, a reliability-ordered initial-state estimator is designed for the tail-biting list decoder, which helps to alleviate the computational burden while retaining the optimal error-correction performance. In conjunction with the optimizations on underlying structures, the proposed list decoder achieves better energy efficiency than existing work under the same coding gain. In the MTC scenario, moreover, the proposed design will be less area consuming than existing schemes to fulfill coding gain enhancement.

Architecture for parallel marker-free variable length streams decoding

Due to throughput requirements above 1 gigapixel/sec for the real-time compression of modern image and video data streams, parallelism for encoding and decoding is inevitable. To achieve parallel decoding, a well-established technique is to insert markers into the variable length code (VLC) stream. By locating markers, it is then possible to extract the sub-streams that are, in turn, decoded in parallel. The use of markers adversely affects compression especially when a high degree of parallelism is required. In this paper, we propose an architecture of a marker-free parallel decoding approach of VLC streams. Instead of multiple local entropy decoders, the proposed architecture is based on using a single parallel entropy decoder in conjunction with a novel format to construct the VLC stream. The approach runs at high clock rates supporting parallelism to a high number of decoders. A synthesized clock frequency well above 110 MHz is achieved for up to 20 decoders on a medium-sized FPGA.

Come and Be Served: Parallel Decoding for COTS RFID Tags

Current commodity RFID systems incur high communication overhead due to severe tag-to-tag collisions. Although some recent works have been proposed to support parallel decoding for concurrent tag transmissions, they require accurate channel measurements, tight tag synchronization, or modifications to standard RFID tag operations. In this paper, we present BiGroup , a novel RFID communication paradigm that allows the reader to decode the collision from multiple commodity-off-the-shelf (COTS) RFID tags in one communication round. In BiGroup , COTS tags can directly join ongoing communication sessions and get decoded in parallel. The collision resolution intelligence is solely put at the reader side. To this end, BiGroup examines the tag collisions at RFID physical layer from constellation domain as well as time domain, exploits the under-utilized channel capacity due to low tag transmission rate, and leverages tag diversities. We implement BiGroup with USRP N210 software radio that is able to read and decode multiple concurrent transmissions from COTS passive tags. Our experimental study gives encouraging results that BiGroup greatly improves RFID communication efficiency, i.e., 11 times performance improvement compared with the alternative decoding scheme for COTS tags.

A novel architecture for parallel multi-view HEVC decoder on mobile device

The multi-view HEVC (MV-HEVC) extension was finalized in July of 2014 by the Moving Picture Experts Group and the Video Coding Experts Group. Recently, multi-view videos based on stereo representations are becoming widely popular. Also, a variety of multimedia contents are now available for mobile devices. A real-time multi-view video decoder is therefore needed. In mobile devices, a real-time decoding multi-view video is difficult because of the increasing number of views, spatial resolutions, and limited speed of the processors on mobile platforms. In this paper, we propose a novel architecture for a real-time decoder in mobile devices. The proposed MV-HEVC decoder uses parallel-optimized multi-view video decoding with multi-threading, using advanced reduced instruction set computer machine (ARM) Cortex multi-core processors. Moreover, it is optimized in single instruction multiple data for an ARM platform. The proposed multi-core decoding architectures enable multi-threading with minimum processing overhead. Experimental results show that the proposed multi-view video coding increased the speed by around 2.4–4.8 times in the ARM platform compared to MV-HEVC.

GHEVC: An Efficient HEVC Decoder for Graphics Processing Units

The high compression efficiency that is provided by the high efficiency video coding (HEVC) standard comes at the cost of a significant increase of the computational load at the decoder. Such an increased burden is a limiting factor to accomplish real-time decoding, specially for high definition video sequences (e.g., Ultra HD 4K). In this scenario, a highly parallel HEVC decoder for the state-of-the-art graphics processor units (GPUs) is presented, i.e., GHEVC. Contrasting to our previous contributions, the data-parallel GHEVC decoder integrates the whole decompression pipeline (except for the entropy decoding), both for intra- and interframes. Furthermore, its processing efficiency was highly optimized by keeping the decompressed frames in the GPU memory for subsequent inter frame prediction. The proposed GHEVC decoder is fully compliant with the HEVC standard, where explicit synchronization points ensure the correct HEVC module execution order. Moreover, the GPU-based HEVC decoder is experimentally evaluated for different GPU devices, an extensive range of recommended HEVC configurations and video sequences, where an average frame rate of 145, 318, and 605 frames per second for Ultra HD 4K, WQXGA, and Full HD, respectively, was obtained in the Random Access configuration with the NVIDIA GeForce GTX TITAN X GPU.

Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.

Non-Uniform Window Decoding Schedules for Spatially Coupled LDPC Codes

Spatially coupled low-density parity-check codes can be decoded using a graph-based message passing algorithm applied across the total length of the coupled graph. However, considering practical constraints on decoding latency and complexity, a sliding window decoding approach is normally preferred. In order to reduce decoding complexity compared with standard parallel decoding schedules, serial schedules can be applied within a decoding window. However, uniform serial schedules within a window do not provide the expected reduction in complexity. Hence, we propose non-uniform schedules (parallel and serial) based on measured improvements in the estimated bit error rate (BER). We show that these non-uniform schedules result in a significant reduction in complexity without any loss in performance. Furthermore, based on observations made using density evolution, we propose a non-uniform pragmatic decoding schedule (parallel and serial) that does not require any additional calculations (e.g., BER estimates) within the decoding process.

Concurrent vs. Exclusive Reading in Parallel Decoding of LZ-Compressed Files

Broadcasting a message from one to many processors in a network corresponds to concurrent reading on a random access shared memory parallel machine. Computing the trees of a forest, the level of each node in its tree and the path between two nodes are problems that can easily be solved with concurrent reading in a time logarithmic in the maximum height of a tree. Solving such problems with exclusive reading requires a time logarithmic in the number of nodes, implying message passing between disjoint pairs of processors on a distributed system. Allowing concurrent reading in parallel algorithm design for distributed computing might be advantageous in practice if these problems are faced on shallow trees with some specific constraints. We show an application to LZC (Lempel-Ziv-Compress)-compressed file decoding, whose parallelization employs these computations on such trees for realistic data. On the other hand, zipped files do not have this advantage, since they are compressed by the Lempel–Ziv sliding window technique.

A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.

A High-Throughput FPGA Architecture for Joint Source and Channel Decoding

In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding are required by the emerging new video transmission applications, such as the first-person remote control of unmanned vehicles. The recently proposed unary error correction (UEC) code facilitates the joint source and channel coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless channel. In this paper, we propose the first hardware implementation of the UEC code that achieves the high processing throughputs as well as ultra-low processing latencies required. This is achieved by extending the application of the recently proposed fully parallel turbo decoder (FPTD) from pure stand-alone channel coding to JSCC. This paper also proposes several novel improvements to the FPTD, in order to increase its hardware efficiency and supported frame length. We demonstrate the application of these improvements to both the long term evolution turbo code and the UEC code. We synthesize the proposed fully parallel design on a mid-range field programmable gate array, achieving a throughput of 450 Mbps, as well as a factor of 2.4 hardware efficiency improvement over previous implementations of the FPTD.

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.

OpenCL을 활용한 CPU와 GPU 에서의 CMMB LDPC 복호기 병렬화

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Objective: VLSI implementation of Decoder Architecture for high throughput using LDPC codes. Methods/Analysis: In this paper, the VLSI architecture of layered partial parallel soft decoding algorithm based decoder for different code size is presented. Findings: LDPC codes provide remarkable error detection performance. Proposed decoder is well matched for VLSI implementation and it is implemented on Xilinx FPGA family. LDPC codes are well-known linear block codes. The computational complexity of LDPC codes is very high as compared to other existing codes like Convolutional codes and Turbo codes. The major benefit is that they offer an enhanced performance, which is very close to the Shannon’s capacity for many different channels and complex algorithms for decoding Novelty/Improvement: By using layered partial parallel soft decoding algorithm, we proposed a pipelined structure that is helpful to achieve higher throughput. The proposed architecture is implemented and tested on FPGA Virtex-5 family with device as 5XC5VLX85. The decoder can attain a throughput of 1.5 Gbps with reduced hardware resources.

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems

Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.

Efficient parallelization using rank convergence in dynamic programming algorithms

This paper proposes an efficient parallel algorithm for an important class of dynamic programming problems that includes Viterbi, Needleman--Wunsch, Smith--Waterman, and Longest Common Subsequence. In dynamic programming, the subproblems that do not depend on each other, and thus can be computed in parallel, form stages, or wavefronts. The algorithm presented in this paper provides additional parallelism allowing multiple stages to be computed in parallel despite dependences among them. The correctness and the performance of the algorithm relies on rank convergence properties of matrix multiplication in the tropical semiring, formed with plus as the multiplicative operation and max as the additive operation. This paper demonstrates the efficiency of the parallel algorithm by showing significant speedups on a variety of important dynamic programming problems. In particular, the parallel Viterbi decoder is up to 24× faster (with 64 processors) than a highly optimized commercial baseline.<!-- END_PAGE_1 -->

비대칭 멀티코어 시스템 상의 HEVC 병렬 디코딩 최적화를 위한 타일 분할 기법

최근 비디오 시스템은 초고해상도 영상의 사용으로 병렬처리의 필요성이 대두되고 있고, 시스템은 ARM big.LITTLE 같은 비대칭 처리능력을 지닌 컴퓨팅 시스템이 도입되고 있다. 따라서, 이 같은 비대칭 컴퓨팅 환경에 최적화된 초고해상도 UHD 비디오 병렬처리 기법이 필요한 시점이다. 본 논문은 인코딩/디코딩 시에 비대칭 컴퓨팅 환경에 최적화 된 HEVC 타일(Tile) 분할 기법을 제안한다. 제안하는 방식은 (1) 비대칭 CPU 코어들의 처리능력과 (2) 비디오 크기별 연산 복잡도 분석 모델을 분석하여, (3) 각 코어에 최적화된 크기의 타일을 할당함으로써, 처리속도가 빠른 CPU 코어와 느린 코어의 인코딩/디코딩 시간차를 최소화한다. 이를 ARM기반의 비대칭 멀티코어 플랫폼에서 4K UHD 표준 영상을 대상으로 실험하였을 때, 평균 약 20%의 디코딩 시간 개선이 발생함을 확인하였다.

Register Free Polar Codes Based Partially Parallel Encoder and Decoder Architecture

This paper presents about the partially parallel encoder and decoder architecture for polar-codes using register-free technique. In this paper, the folding transformation technique and register minimization technique are used for this architecture to reduce the circuit and timing complexity. In general, the polar codes are referred to a low complexity code to achieve the performance of channel carrying capacity in a binary-input memory-less channels. In the fully-parallel architecture, the hardware complexity is the major drawback which is high whereas in partially-parallel architecture the memory-sharing concept is utilized to overcome the complexity of hardware to attain the high throughput application. Thus, the temporary end results are saved within the registers instead of memories and multiplexers to manage the interlocking wires. Hence, the register aspect in polar code centered encoder and decoder architecture are eliminated. In an effort to support the information transmission efficiency stage, we get rid of the knowledge storage side (d-register) in stage-three and stage-four encoder and decoder method. Finally we reduce the 32 register elements for every data transmission process and mainly focus on the data storage and transmit function. Because the storage events are need to more time for data passing to one stage level to another stage.

LTE Turbo Decoding Parallel Architecture with Single Interleaver Implemented on FPGA

This paper describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP Long-Term Evolution standard. Considering the high data rates required by this standard, parallel decoding architecture is used. The parallel decoding latency is reduced N times compared with the serial decoding latency, N being the parallelization factor, usually a power of 2. The decoding performances are similar for both serial and parallel schemes, when very low decoding latency is added to this theoretical parallel latency value. Taking advantage of the quadratic permutation polynomial interleaver properties, and considering some specific FPGA block memory characteristics, a novel simplified parallel decoding scheme is proposed, including only one interleaver, independently of the N value. Moreover, for the single interleaver, we propose a solution that exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. In addition, an even-odd merge sorting network provides correct data to all N decoding units.

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.