Parallel Decoding Research Articles

Stochastic resonance in parallel concatenated turbo code decoding

In an array of threshold devices, we examine the effect of noise in improving performance of turbo code decoding. Such a phenomenon of noise-enhanced effect is termed stochastic resonance (SR). When signal is subthreshold, SR is observed by using Gaussian noise during iterative decoding. That is, the minimal bit error ratio (BER) is achieved at some non-zero noise intensity level. Besides, the larger the number of threshold devices is, the more remarkable the SR effect becomes. Especially when noise intensity is nearly optimal, BER approximates to zero after a few decoding iterations. Moreover, when Gaussian mixture noise is utilized, suprathreshold stochastic resonance (SSR) occurs in turbo decoding. These results show the beneficial effect of noise in channel coding and decoding.

Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems

This manuscript proposes three classes of codes for error correction in a storage system in which the memory cells do not have the same number of levels, i.e., a multiscale storage. The proposed codes are single multiscale-symbol error correction (SMSEC) codes and are capable of correcting any errors occurring on a single memory cell, namely a column-deleted SMSEC code, an element-compacted SMSEC code and a product SMSEC code. In the proposed codes, the codewords are divided into two partitions, the elements on the first partition are over GF(2 b 1), while those on the remaining partition are over GF(2 b 2). This paper also gives guidelines for selection among the three SMSEC codes to meet the desired hardware overhead in the parallel decoder for realistic parameters of the partition pair, such as ( b 1, b 2) = (4,3), (4,2) and (3,2). Moreover it is shown that the best choice for a MSS system is the SMSEC code with the shortest check bit length; if the check bit lengths of at least two codes are equal, then the use of the element-compacted SMSEC code incurs in the smallest hardware overhead.

Efficient Non-Recursive Design of Second-Order Spectral-Null Codes

A new efficient design of second-order spectral-null (2-OSN) codes is presented. The new codes are obtained by applying the technique used to design parallel decoding balanced (i.e., 1-OSN) codes to the random walk method introduced by some of the authors for designing 2-OSN codes. This gives new non-recursive efficient code designs, which are less redundant than the code designs found in the literature. In particular, if $k \in {\mathrm{I}}\mskip -2.5mu{\mathrm{I}}\mskip -7mu{\mathrm{N}} $ is the length of a 1-OSN code then the new 2-OSN coding scheme has length $n=k+r \in {\mathrm{I}}\mskip -2.5mu{\mathrm{I}}\mskip -7mu{\mathrm{N}} $ with an extra redundancy of $r\simeq 2\log _{2}k+(1/2)\log _{2}\log _{2} k-0.174$ check bits, with $k$ and $r$ even and $n$ multiple of 4. The whole coding process requires $O(k\log k)$ bit operations and $O(k)$ bit memory elements.

Data Detection Algorithms for BICM Alternate-Relaying Cooperative Systems With Multiple-Antenna Destination

This paper proposes two new data detection algorithms for decode-and-forward alternate-relaying cooperative communication systems. These algorithms are discussed in the context of bit-interleaved coded modulation transmission with a multiple-antenna destination. The interference signal, resulting from the concurrent transmission of the source and one of the relays, is exploited as a beneficial resource to develop an optimal data detection algorithm. We show that the optimal algorithm can be implemented by parallel demappers, each based on a family of Bahl, Cocke, Jelinek, and Raviv algorithms, connected to parallel decoders in an iterative way. Due to the need to buffer the entire frame before decoding, the optimal algorithm suffers from long processing time. A suboptimal algorithm is also proposed to avoid this problem, where each packet is decoded by using two consecutive received packets. The suboptimal algorithm reduces processing time, complexity, bandwidth loss, and memory size with a slight increase in the bit error rate (BER). The BER performance of the proposed algorithms is evaluated via Monte Carlo simulations, and the results indicate their effectiveness in improving the BER performance.

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

Memories that operate in harsh environments, like for example space, suffer a significant number of errors. The error correction codes (ECCs) are routinely used to ensure that those errors do not cause data corruption. However, ECCs introduce overheads both in terms of memory bits and decoding time that limit speed. In particular, this is an issue for applications that require strong error correction capabilities. A number of recent works have proposed advanced ECCs, such as orthogonal Latin squares or difference set codes that can be decoded with relatively low delay. The price paid for the low decoding time is that in most cases, the codes are not optimal in terms of memory overhead and require more parity check bits. On the other hand, codes like the (24,12) Golay code that minimize the number of parity check bits have a more complex decoding. A compromise solution has been recently explored for Bose–Chaudhuri–Hocquenghem codes. The idea is to implement a fast parallel decoder to correct the most common error patterns (single and double adjacent) and use a slower serial decoder for the rest of the patterns. In this brief, it is shown that the same scheme can be efficiently implemented for the (24,12) Golay code. In this case, the properties of the Golay code can be exploited to implement a parallel decoder that corrects single- and double-adjacent errors that is faster and simpler than a single-error correction decoder. The evaluation results using a 65-nm library show significant reductions in area, power, and delay compared with the traditional decoder that can correct single and double-adjacent errors. In addition, the proposed decoder is also able to correct some triple-adjacent errors, thus covering the most common error patterns.

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

This paper presents an optimized parallel algorithm for the next-generation video codec High Efficiency Video Coding (HEVC). The proposed method provides maximized parallel scalability by exploiting two levels of parallelism: 1) frame level and 2) task level. Frame-level parallelism is exploited using a graph that efficiently provides a parallel coding order of the frames with complex reference dependencies. The proposed reference dependency graph is generated at runtime by a novel construction algorithm that dynamically analyzes the configuration of the HEVC codec. Task-level parallelism is exploited to provide further scalability to frame-level parallelization. A pipelined execution is allowed for independent tasks, which are defined by dividing and categorizing a single coding process into multiple types of tasks. The proposed parallel encoder and decoder do not suffer from loss in coding efficiency because neither constraints nor modification in coding options are required. The proposed parallel methods result in an average encoding speedup of 1.75 and the aggressive method that exploits additional frame-level parallelism achieved 6.52 speedup using eight physical cores.

MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계

MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계

On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling

With the emergence of the High Efficiency Video Coding (HEVC) standard, a dataflow description of the decoder part was developed as part of the MPEG-B standard. This dataflow description presented modest framerate results which led us to propose methodologies to improve the performance. In this paper, we introduce architectural improvements by exposing more parallelism using YUV and frame-based parallel decoding. We also present platform optimizations based on the use of SIMD functions and cache efficient FIFOs. Results show an average acceleration factor of 5.8 in the decoding framerate over the reference architecture.

High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes

This paper presents a novel construction scheme for nonbinary single-error correcting (SEC) codes that yields high-speed parallel decoding. The proposed scheme utilizes two methods, namely, Improved and Reordered; these methods can be also combined. Both of these methods reduce the number of 1's in the parity-check matrix (H-matrix) by reducing the 1's in every row vector. This results in a reduction in the gate depth in the syndrome generator, thus achieving a shorter delay time for parallel decoding. In the proposed Improved method, for a single $b$ -bit byte (i.e., $\mbox{2}^{b}$ -ary symbol) error correcting code, the submatrix of the H-matrix corresponding to every $b$ -bit byte is multiplied with a regular matrix. The so-called improved submatrix is generated using a heuristic (greedy) algorithm. The proposed Reordered method selects the correct $b$ -bit bytes for deletion when shortening is performed. Simulation results show that the proposed scheme accomplishes a faster parallel decoding time than existing schemes. Furthermore, the proposed scheme is applicable to any class of linear SEC codes, whereas existing schemes are applicable only to specific codes. Extensive simulation results are provided to substantiate the viability of the proposed codes for faster parallel decoding (albeit incurring for most cases in modest increases of area and power dissipation due to additional circuitry).

다중 채널 부호를 이용한 FTN 전송 시스템

FTN (Faster Than Nyquist) 전송 방식은 나이퀴스트 (Nyquist) 율보다 빠르게 신호를 전송할 수 있으나 필연적으로 ISI (Inter-Symbol Interference)가 발생하고 이로 인하여 송신 심볼 간 상관관계가 발생한다. 한편 터보류 채널 부호화 방식에서는 정보 프레임의 길이가 길어질수록 성능이 개선되나 정보 프레임의 길이가 길어짐에 따라 전송 지연, 복호기의 복잡도 및 복호 지연이 증가하는 문제가 있다. 본 논문에서는 FTN 전송으로 인하여 발생한 심볼 간 상관관계를 활용하여 부호어 (codeword)들 간에 상관관계를 부여하고 이를 통하여 보다 큰 정보 프레임을 사용하는 것과 같은 효과를 제공할 수 있는 기법을 제안한다. 제안하는 기법은 부호어 간 상관관계로 인하여 보다 큰 정보 프레임을 사용하는 것과 유사한 성능을 나타낼 뿐만 아니라 복호기에서는 다수의 구성 복호기 (constituent decoder)가 병렬로 연결된 구조를 갖고 있어 병렬 복호가 용이한 장점이 있다. The performance of turbo-like codes highly depends on their frame size and thus, the bit error rate performance of turbo-like codes can be improved by increasing the frame size. Unfortunately, increasing the frame size of channel codes induces some drawbacks such as the increase of not only encoding and decoding complexity but also transmission and decoding latencies. On the other hand, a faster than Nyquist (FTN) transmission causes intentional inter-symbol interference (ISI) and thus, induces some correlation among the transmission symbols. In this paper, we propose an FTN transmission with multiple channel codes. By exploiting the correlation among the modulated symbols, multiple code frames can be regarded as a code frame with a lager frame size. Due to the inherent parallel encoding scheme of proposed scheme, parallel decoding can be easily implemented.

Low-Rank Methods for Parallelizing Dynamic Programming Algorithms

This article proposes efficient parallel methods for an important class of dynamic programming problems that includes Viterbi, Needleman-Wunsch, Smith-Waterman, and Longest Common Subsequence. In dynamic programming, the subproblems that do not depend on each other, and thus can be computed in parallel, form stages or wavefronts . The methods presented in this article provide additional parallelism allowing multiple stages to be computed in parallel despite dependencies among them. The correctness and the performance of the algorithm relies on rank convergence properties of matrix multiplication in the tropical semiring, formed with plus as the multiplicative operation and max as the additive operation. This article demonstrates the efficiency of the parallel algorithm by showing significant speedups on a variety of important dynamic programming problems. In particular, the parallel Viterbi decoder is up to 24× faster (with 64 processors) than a highly optimized commercial baseline.

Design of QPP Interleavers for the Parallel Turbo Decoding Architecture

Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increasing data rates motivated by throughput-intensive applications result in higher parallelism of turbo decoder design, rendering the efficient realization of the interleaver a highly challenging work. This paper addresses the design of quadratic permutation polynomial (QPP) interleaver for the symbol-based serial MAP (SMAP) and the cross MAP (XMAP) parallel decoding. To circumvent the access conflicts incurred by the randomness of the interleaving function, the stratssonably position soft outputs of maximum a-posteriori (MAP) decoders in memory instances is firstly investigated. On this basis, a hardware-friendly parallel interleaver architecture is proposed by utilizing the algebraic properties of QPP function. Theoretical evaluation and experimental results demonstrate that the proposed design gains boosted hardware efficiency compared to existing schemes, and is applicable to both SMAP and XMAP decoding with arbitrary parallelism.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

VLSI Implementation of Fully Parallel LTE Turbo Decoders

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.

Insertion Algorithms with Justification for Solving the Resource-Constrained Project Scheduling Problem

The paper presents the resource-constrained project scheduling problem with the makespan minimisation criterion. To solve the problem, the authors propose insertion algorithms which generate schedules with use of forward serial and parallel decoding procedures. Schedules are improved with the use of the double justification by extremes technique (first right and then left justification). The efficiency of the procedures proposed is tested on standard test problems from the PSPLIB library.

Parallel decoding for lattice reduction-aided MIMO Receiver

Parallel decoding for lattice reduction-aided MIMO Receiver

4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions

Two High Efficiency Video Coding (HEVC) extensions, namely, the scalable HEVC (SHVC) extension and multiview HEVC (MV-HEVC) extension, have been finalized in July 2014 by the Moving Picture Experts Group and Video Coding Experts Group. These two extensions enable additional features not covered in the first version of the HEVC standard such as spatial, fidelity, bitdepth, and color gamut scalability, as well as stereoscopic and multiview representations. In this paper, we propose a software parallel decoder architecture for the HEVC standard and its multilayer extensions, including SHVC and MV-HEVC extensions. The decoder consists of multiple instances of the OpenHEVC decoder, one instance to decode each layer with a communication between dependent layers to perform inter-layer predictions. The proposed multilayer HEVC decoder is parallel friendly and supports both wavefront parallelism to simultaneously process adjacent rows of the frame and frame-based parallelism to decode a set of temporal and spatial frames in parallel. Moreover, the most time-consuming operation introduced in the SHVC extension, namely, the resampling of the inter-layer reference picture in spatial scalability, is optimized in single instruction multiple data for x86 platform. We assess the complexity of the multilayer HEVC decoder with respect to the simulcast configuration. The multilayer decoder decoding two SHVC layers introduces in average 40%–71% additional complexity compared with the single layer HEVC decoder. Moreover, the low level optimizations with a hybrid parallel processing solution enable a real-time decoding of 4Kp60 enhancement layer on a 6-core Intel i7 processor running at 3.4 GHz.

Decoding the view expectation during learned maze navigation from human fronto-parietal network.

Humans use external cues and prior knowledge about the environment to monitor their positions during spatial navigation. View expectation is essential for correlating scene views with a cognitive map. To determine how the brain performs view expectation during spatial navigation, we applied a multiple parallel decoding technique to functional magnetic resonance imaging (fMRI) when human participants performed scene choice tasks in learned maze navigation environments. We decoded participants’ view expectation from fMRI signals in parietal and medial prefrontal cortices, whereas activity patterns in occipital cortex represented various types of external cues. The decoder’s output reflected participants’ expectations even when they were wrong, corresponding to subjective beliefs opposed to objective reality. Thus, view expectation is subjectively represented in human brain, and the fronto-parietal network is involved in integrating external cues and prior knowledge during spatial navigation.

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes

Approximate (or inexact) computing is an attractive paradigm for digital processing at nanometric scales for applications in which imprecision in computation can be tolerated for improvements in other computational figures of merit, such as power consumption, circuit complexity and delay. The same principles of approximate computing are investigated in this manuscript for storage protection using an unequal protection code (UEP). In the proposed UEP code, the codeword is divided into two partitions; these partitions have different error protection functions. This paper presents a new class of two-level burst error correcting UEP codes and its parallel decoder. The proposed code is more efficient than an existing code in term of code rate, area and power consumption for the parallel decoder.