Parallel Dataflow Research Articles

Computational architectures for sonar array processing in autonomous rovers

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures.

Analysis and classification of flow-carrying backbones in two-dimensional lattices

The paper proposes a new data-flow based approach for the identification of backbones in infinite clusters on 2-D percolation site lattices of dimension L × L. The infinite cluster is identified first, then a multi step algorithm is applied for the reduction of the infinite cluster to its backbone. Algorithm performances are evaluated theoretically and experimentally. The algorithm is local and can therefore be efficiently implemented on data-flow parallel platforms in Θ(L) time if applied on percolation lattices near the critical percolation probability or in Θ(L2) in the worst case. The proposed methodology could resolve the problem of stack overflow at large systems that can appear with classical graph based algorithms, and has potential for a higher execution speed-up on parallel architectures.

Energy-Awareness and Performance Management with Parallel Dataflow Applications

Applications have traditionally been executed as fast as possible (Race-to-Idle) and mapped to as many cores as possible (Fair scheduling) to minimize the energy consumption. With modern hardware, this method has become inefficient because of the power characteristics of the platforms. Instead, applications should utilize an optimal combination of clock frequency and number of cores to balance the dynamic and static power. Such approaches have been difficult to achieve since resource allocation is based only on CPU utilization. Resources are then allocated to prohibit over utilization rather than following software performance requirements. By adjusting the clock frequency directly according to software requirements and activating CPU cores according to the application parallelism, significant energy can be saved by lowering the average power dissipation. To enforce these recommendations, this paper provides means of expressing performance and parallelism in applications for more tight integration with the power management to balance the execution speed and mapping on multi-core systems. An interface between the applications and the hardware resources is provided in combination with a novel power management runtime system called Bricktop. A signal processing case study demonstrates real-world energy savings up to 50 % without performance degradation.

A High-Throughput Low-Complexity Radix-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {4}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {2}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {3}}$ </tex-math></inline-formula> FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems

This brief presents a high-throughput low-complexity 512-point fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) processor for IEEE 802.11ad standard aiming at the wireless personal area network applications. To reduce the complexity of twiddle factor multiplication, the radix- $\boldsymbol {2^{4}}$ - $\boldsymbol {2^{2}}$ - $\boldsymbol {2^{3}}$ FFT algorithm is devised. To achieve the throughput of 1.76 GS/s (which is normalized as eight samples/clock) and meet the frame format of single carrier as well as orthogonal frequency division multiplexing physical layer that no interval is inserted between any two 512-length data blocks in a frame, the mixed-radix multipath delay feedback structure is adopted to support the continuous data flow. Moreover, we propose a novel reorder scheme to support parallel normal-order output data flow continuously, which demands only a single-RAM-group, i.e., 512-word memory size with very simple control logic. Overall, the whole FFT/IFFT processor is high throughput and area efficient, and the back-end simulation results show that the core area of the FFT processor is 1.69 $\mathrm{mm}^{2}$ in Silterra 0.13 ${\mu }$ m process.

Automation of Formal Verification of Programs in the Pifagor Language

Nowadays, due to software sophistication, programs correctness is more often proved by means of formal verification. The method of deduction based on Hoare logic could be used for any programming language and it has the capability of partial automation of the proof process. However, the method of deduction is not widely used for verification of parallel programs because of high complexity of the process. The usage of the functional data-flow paradigm of parallel programming allows to decrease the complexity of the proof process. In this article a proof process of correctness of functional data-flow parallel programs in the Pifagor language is considered. The proof process of a program correctness is considered as a tree where each node is a program data-flow graph, whose edges are marked with formulas in a specification language. The tree root is the initial program data-flow graph with a precondition and a postcondition, which describe restrictions on input variables and correctness conditions of the result of the program execution, respectively. Basic transformations of the data-flow graph are edge marking, equivalent transformation, splitting, folding of the program. By means of these transformations the data-flow graph is transformed and finally is reduced to a set of formulas in the specification language. If all these formulas are identically true, the program is correct. Several modules is distinguished in the system: “Program correctness prover”, “Axioms and theorems library management system” and “Errors analysis and output of information about errors”. According to this architecture, the toolkit for supporting formal verification was developed. The main functionality of the system implementation is considered.

New readout and data-acquisition system in an electron-tracking Compton camera for MeV gamma-ray astronomy (SMILE-II)

For MeV gamma-ray astronomy, we have developed an electron-tracking Compton camera (ETCC) as a MeV gamma-ray telescope capable of rejecting the radiation background and attaining the high sensitivity of near 1mCrab in space. Our ETCC comprises a gaseous time-projection chamber (TPC) with a micro pattern gas detector for tracking recoil electrons and a position-sensitive scintillation camera for detecting scattered gamma rays. After the success of a first balloon experiment in 2006 with a small ETCC (using a 10×10×15cm3 TPC) for measuring diffuse cosmic and atmospheric sub-MeV gamma rays (Sub-MeV gamma-ray Imaging Loaded-on-balloon Experiment I; SMILE-I), a (30cm)3 medium-sized ETCC was developed to measure MeV gamma-ray spectra from celestial sources, such as the Crab Nebula, with single-day balloon flights (SMILE-II). To achieve this goal, a 100-times-larger detection area compared with that of SMILE-I is required without changing the weight or power consumption of the detector system. In addition, the event rate is also expected to dramatically increase during observation. Here, we describe both the concept and the performance of the new data-acquisition system with this (30cm)3 ETCC to manage 100 times more data while satisfying the severe restrictions regarding the weight and power consumption imposed by a balloon-borne observation. In particular, to improve the detection efficiency of the fine tracks in the TPC from ~10% to ~100%, we introduce a new data-handling algorithm in the TPC. Therefore, for efficient management of such large amounts of data, we developed a data-acquisition system with parallel data flow.

Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform

The introduction of multi-core processors has renewed the interest in programming models which can efficiently exploit general purpose parallelism. Data-Flow is one such model which has demonstrated significant potential in the past. However, it is generally associated with functional styles of programming which do not deal well with shared mutable state. There have been a number of attempts to introduce state into Data-Flow models and functional languages but none have proved able to maintain the simplicity and efficiency of pure Data-Flow parallelism. Transactional memory is a concurrency control mechanism that simplifies sharing data when developing parallel applications while at the same time promises to deliver affordable performance. In this paper we report our experience of integrating Transactional Memory and Data-Flow within the TFlux Platform. The ability of the Data-Flow model to expose large amounts of parallelism is maintained while Transactional Memory provides simplified sharing of mutable data in those circumstances where it is important to the expression of the program. The isolation property of transactions ensures that the exploitation of Data-Flow parallelism is not compromised. In this study we extend the TFlux platform, a Data-Driven Multi-threading implementation, to support transactions. We achieve this by proposing new pragmas that allow the programmer to specify transactions. In addition we extend the runtime functionality by integrating a software transactional memory library with TFlux. To test the proposed system, we ported two applications that require transactional memory: Random Counter and Labyrinth an implementation of Lee's parallel routing algorithm. Our results show good opportunities for scaling when using the integration of the two models.

Инструментальная поддержка формальной верификации программ, написанных на языке функционально-потокового параллельного программирования

The article is devoted to the architecture development of the toolkit for supporting formal verification of functional data-flow parallel programs in the Pifagor Language. The method of deduction based on Hoare logic is used for formal verification. A proof process is considered as a tree where each node is a program data-flow graph, whose edges are marked with formulas in a specification language. The tree root is the initial Hoare triple, namely the program data-flow graph with a precondition and a postcondition. In this article basic transformations of the data-flow graph are considered: edge marking, equivalent transformation, splitting, folding of the program. By means of these transformations the initial triple is being transformed and finally is reduced to a set of formulas in the specification language. If all of these formulas are identically true, then the program is correct. Architecture of the toolkit for supporting formal verification of functional data-flow parallel programs is proposed, which allows to construct a proof three. The implementation of the toolkit is introduced and its main functionality is considered.

Formal Verification of Programs in Functional Dataflow Parallel Language

The article is devoted to the methods of proving parallel programs correctness that are based on the axiomatic approach. Formal system for functional data-flow parallel programming language Pifagor is described. On the basis of this system programs correctness could be proved.

Tail Recursion Transformation in Functional Dataflow Parallel Programs

The peculiarities of transforming functional dataflow parallel programs into programs with finite resources are analysed. It is considered how these transformations are affected by the usage of asynchronous lists, the return of delayed lists and the variation of the data arrival pace relative to the time of its processing. These transformations allow us to generate multiple programs with static parallelism based on one and the some functional dataflow parallel program.

A functional unit network for rapid, low-power loop execution

Computer architects have focused on advanced processor designs that achieve high performance through multiple cores and multiple threads, and at the same time keep power dissipation low. In this work, we propose a processor back end, specifically designed for rapid loop execution and low power dissipation. This back end consists of a network of functional unit nodes, in which instructions of the loop body are issued only once until loop completion. In this way, we exploit both instruction-level and data-flow parallelism. We attempt to decrease power consumption by turning off the front end and all unused functional units. Simulation results show that the proposed back end can accelerate Livermore loops by up to N/k, for a network of N units and loop body size of N instructions, and an issue rate of k instructions per cycle, when compared to scalar or superscalar RISC execution.

Принципы организации системы ввода/вывода параллельной потоковой вычислительной системы

Принципы организации системы ввода/вывода параллельной потоковой вычислительной системы

Cluster-to-cluster data transfer with data compression over wide-area networks

The recent emergence of ultra high-speed networks up to 100 Gb/s has posed numerous challenges and has led to many investigations on efficient protocols to saturate 100 Gb/s links. However, end-to-end data transfers involve many components, not only protocols, affecting overall transfer performance. These components include disk I/O subsystem, additional computation associated with data streams, and network adapters. For example, achievable bandwidth by TCP may not be implementable if disk I/O or CPU becomes a bottleneck in end-to-end data transfer. In this paper, we first model all the system components involved in end-to-end data transfer as a graph. We then formulate the problem whose goal is to achieve maximum data transfer throughput using parallel data flows. We also propose a variable data flow GridFTP XIO stack to improve data transfer with data compression. Our contributions lie in how to optimize data transfers considering all the system components involved rather than in accurately modeling all the system components involved. Our proposed formulations and solutions are evaluated through experiments on the ESnet 100G testbed and a wide-area cluster-to-cluster testbed. The experimental results on the ESnet 100G testbed show that our approach is several times faster than Globus Online—8 × faster for datasets with many 10 MB files and 3–4 × faster for other datasets of larger size files. The experimental results on the cluster-to-cluster testbed show that our variable data flow approach is up to 4 × faster than a normal cluster data transfer.

Tail recursion transformation in functional dataflow parallel programs

The peculiarities of transforming functional dataflow parallel programs into programs with finite resources are analysed. It is considered how these transformations are affected by the usage of asynchronous lists, the return of delayed lists and the variation of the data arrival pace relative to the time of its processing. These transformations allow us to generate multiple programs with static parallelism based on one and the same functional dataflow parallel program.

Formal verification of programs in the functional data-flow parallel language

The article is devoted to the methods of proving parallel programs correctness, that are based on the axiomatic approach. Formal system for functional data-flow parallel programming language Pifagor is described. On the basis of this system programs correctness could be proved.

Improving fairness in IEEE 802.11 networks using MAC layer opportunistic retransmission

This paper introduces DAFMAC (Decode And Forward MAC), a scalable opportunistic cooperative retransmission enhancement for the IEEE 802.11 MAC protocol which operates without the need for additional explicit control signalling. Distributed opportunistic retransmission algorithms rely on selecting a single suitable relay without direct arbitration between nodes. Simulations show that DAFMAC offers a significant improvement in fairness for both throughput and jitter, giving multiple parallel data flows a more equal opportunity to utilise the channel. DAFMAC cooperative retransmissions are shown to reduce node energy consumption for a given throughput. Further, the DAFMAC relay selection algorithm is shown to scale very well in terms of complexity and memory requirements in comparison to other cooperative retransmission schemes.

The Design of Acquisition System of Compact Seismic Recorder

At present, seismic exploration, as a commonly used geophysical method has been widely applied in the field of resource exploration. Combined with the special application environment, based on the techniques of 24bit Δ- ΣA/D, multi-channel seismograph acquisition system is realized by the 24bit Δ- Σ conversion chip CS5340; design the related circuits with FPGA, reading and caching the serial output data of D/A and converting to parallel dataflow, realizing the data transmit to ARM; On the basis of hardware design, we complete the design of the acquisition system monitoring and control software, use the C language designed acquisition software and trigger control software, realize the various instructions of the host via the Ethernet port (Ethernet) transmit to the ARM and complete of the data collection. Last, the prototype has been finished, and the primary test results are given

Turbine: A Distributed-memory Dataflow Engine for High Performance Many-task Applications

Efficiently utilizing the rapidly increasing concurrency of multi-petaflop computing systems is a significant programming challenge. One approach is to structure applications with an upper layer of many loosely coupled coarse-grained tasks, each comprising a tightly-coupled parallel function or program. “Many-task” programming models such as functional parallel dataflow may be used at the upper layer to generate massive numbers of tasks, each of which generates significant tightly coupled parallelism at the lower level through multithreading, message passing, and/or partitioned global address spaces. At large scales, however, the management of task distribution, data dependencies, and intertask data movement is a significant performance challenge. In this work, we describe Turbine, a new highly scalable and distributed many-task dataflow engine. Turbine executes a generalized many-task intermediate representation with automated self-distribution and is scalable to multi-petaflop infrastructures. We present here the architecture of Turbine and its performance on highly concurrent systems.

Fine-Grained Multithreading for the Multifrontal $QR$ Factorization of Sparse Matrices

The advent of multicore processors represents a disruptive event in the history of computer science as conventional parallel programming paradigms are proving incapable of fully exploiting their potential for concurrent computations. The need for different or new programming models clearly arises from recent studies which identify fine-granularity and dynamic execution as the keys to achieving high efficiency on multicore systems. This work presents an approach to the parallelization of the multifrontal method for the $QR$ factorization of sparse matrices specifically designed for multicore based systems. High efficiency is achieved through a fine-grained partitioning of data and a dynamic scheduling of computational tasks relying on a dataflow parallel programming model. Experimental results show that an implementation of the proposed approach achieves higher performance and better scalability than existing equivalent software.

End-to-End Data-Flow Parallelism for Throughput Optimization in High-Speed Networks

The increase in the data produced by large-scale scientific applications necessitates innovative solutions for efficient transfer of data. Although the current optical networking technology reached theoretical speeds of 100 Gbps, applications still suffer from inefficient transport protocols and bottlenecks on the end-systems (e.g. disk, CPU, NIC). High-performance systems provide us with parallel disks, processors and network interfaces. However the lack of orchestration of these end-system resources with the available network capacity results in underutilization of the network bandwidth. In this study, a model and two algorithms that use `end-to-end data-flow parallelism' to optimize the use of network and end-system resources are proposed. This is achieved by using multiple parallel streams over the network; and multiple parallel disks and CPUs at the end systems. Our model predicts the optimal number of streams and disk/CPU stripes that maximizes the data transfer speed for any setting. Our algorithms use GridFTP parallel samplings and calculate the optimal level of parallelism based on our prediction model. The experiments conducted by using actual GridFTP transfers show that the predictions performed by our model and algorithms provide close-to-optimal performances with negligible overhead and use minimal number of resources. The end-to-end data transfer throughput is improved dramatically in existence of end-system bottlenecks compared to the non-optimized transfers.