Parallel-connected Devices Research Articles

Design of Half-Bridge Switching Power Module Based on Parallel-Connected SiC MOSFETs for LLC Resonant Converter with Symmetrical Structure and Low Parasitic Inductance

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

Electrothermal Modelling and Measurements of Parallel-Connected V<sub>TH </sub>Mismatched SiC MOSFETs under Inductive Load Switching

In high current applications that use several parallel-connected SiC MOSFETs (e.g., automotive traction inverters), optimal current sharing is integral to overall system reliability. Threshold voltage (VTH) variation in SiC MOSFETs is a prevalent reliability issue that can cause current mismatch in parallel-connected devices. Using experimental measurements and compact modelling, a technique has been developed for characterising the impact of VTH variation in up to 8 parallel-connected SiC MOSFETs. This model can predict the allowable VTH variation for optimal current sharing. It can also be used to evaluate the impact of other parameters, including gate driver synchronisation, on current sharing in parallel devices.

A 15-kA Solid-State Circuit Breaker Research and Development for the Switch Network Unit of the EAST Tokamak

This article describes the research, development, and testing of a 15-kA solid-state circuit breaker (SSCB) prototype applied to the switch network unit (SNU) of the Experimental Advanced Superconducting Tokamak (EAST). The circuit scheme composed of parallel connected integrated gate-commutated thyristors (IGCTs) and the diode bridge to realize bidirectional breaker ability is presented first. In addition, the stray inductances of the bus bars and the heat sinks for the current sharing of each IGCT are also considered in detail. Through ANSYS Q3D parameters extraction, the influence of structure stray parameters on the current sharing of power device in parallel is analyzed. Finally, the operation performance of the SSCB has been successfully tested up to the rated current of 15 kA and the maximum interruption voltage of about 2.0 kV, these experiment results verified the current sharing of the parallel-connected devices and the reliability of the SSCB during current conduction and current commutation processes.

Impedance-Based Stability Analysis of Paralleled Grid-Connected Rectifiers: Experimental Case Study in a Data Center

Grid-connected systems often consist of several feedback-controlled power-electronics converters that are connected in parallel. Consequently, a number of stability issues arise due to interactions among multiple converter subsystems. Recent studies have presented impedance-based methods to assess the stability of such large systems. However, only few real-life experiences have been previously presented, and practical implementations of impedance-based analysis are rare for large-scale systems that consist of multiple parallel-connected devices. This work presents a case study in which an unstable high-frequency operation, caused by multiple paralleled grid-connected rectifiers, of a 250 kW data center in southern Finland is reported and studied. In addition, the work presents an experimental approach for characterizing and assessing the system stability by using impedance measurements and an aggregated impedance-based analysis. Recently proposed wideband-identification techniques based on binary injection and Fourier methods are applied to obtain the experimental impedance measurements from the input terminals of a single data center rectifier unit. This work provides a practical approach to design and implement the impedance-based stability analysis for a system consisting of multiple paralleled grid-connected converters. It is shown that the applied methods effectively predict the overall system stability and the resonant modes of the system, even with very limited information on the system. The applied methods are versatile, and can be utilized in various grid-connected applications, for example, in adaptive control, system monitoring, and stability analysis.

Predicted annual energy yield of III-V/c-Si tandem solar cells: modelling the effect of changing spectrum on current-matching.

High efficiencies of >30% are predicted for series-connected tandem solar cells when current-matching is achieved between the wide-bandgap top cell and silicon bottom cell. Sub-cells are typically optimized for current-matching based on the standard AM1.5G spectrum, but in practice, the incident radiation on a solar cell can be very different from this standard due to the effects of the sun's location in the sky, atmospheric conditions, total diffuse element etc. The resulting deviations in spectral content from optimum conditions lead to current mismatch between tandem cell layers that adversely affects the device's performance. To investigate the impact of this issue the energy yield (%) of tandem solar cells comprising a III-V wide-bandgap solar cell connected electrically and optically in series with a silicon bottom cell was simulated over a full year using measured spectral data from Denver, CO. Top cells with bandgaps from 1.5-1.9 eV were modelled using an external radiative efficiency method. The predicted annual energy yields were as high as 31% with an optimum 1.8 eV top cell, only 2.8% lower (absolute) than the AM1.5G predicted efficiency. The annual energy yield of tandem cells with no current-matching constraint, i.e. parallel-connected devices, was also simulated. Here the difference between series and parallel connections were only significant for non-optimum bandgap combinations. Our results indicate that AM1.5G based optimization of sub-cells can be effectively employed to achieve high energy yields of >25% for III-V/Si tandem solar cells in mid-latitude US locations, despite the continuous variation in spectra throughout a calendar year.

Device Screening Strategy for Balancing Short-Circuit Behavior of Paralleling Silicon Carbide MOSFETs

This paper studies the spread of key electrical parameters of Silicon Carbide (SiC) MOSFET devices and its effect on the short-circuit (SC) behaviors. Device screening strategies are proposed to reduce the variation of the SC behaviors among the parallel-connected devices. Firstly, thirty discrete SiC devices from same production lot are characterized in terms of threshold voltage, transconductance, and on-resistance. The maximum variations of these device parameters are 0.5V, 1.41S and 25m ${\Omega } $ , respectively. The SC tests are performed individually on each device. The variations of SC peak current, SC energy, and SC junction temperature among these devices are 40A, 0.06J and 77°C. Furthermore, the effect of each parameter on SC behaviors variations is discussed. Based on the offset effect of parameters variation and the single transfer curves variation (TCV), a novel device screening strategy is developed. The variation of SC behavior of paralleling devices can be reduced by using the developed device screening strategy. This paper aims to provide guidelines on device screening for paralleling SiC MOSFETs.

LV Converters: Improving Efficiency and EMI Using Si MOSFET MMC and Experimentally Exploring Slowed Switching

Widespread adoption of electric vehicles will require ac power distribution systems to accommodate high penetrations of power electronic loads, placing increasing demands on the power quality of grid-connected converters. Recent developments in devices and circuit topologies have the potential to improve the intrinsic power quality of these grid interface inverters, reducing the need for passive filters and associated reactive power consumption. Wide bandgap devices, such as SiC, have recently gained much attention due to their low switching losses facilitating raised pulsewidth modulation frequencies. However, the high cost of SiC together with electromagnetic interference (EMI) resulting from very rapid switching transitions necessary to realize low switching losses cause concern. Previous research in Si MOSFET modular multilevel converters (MMC) suggests a high-efficiency alternative with potential for lower EMI. Si MOSFET MMC benefits are enhanced with parallel-connected devices and slowed switching, made possible by low effective switching frequency. This paper uses experimental results to explore the impact of parallel connection and slowed switching on Si MOSFET MMC losses, and presents improved Si MOSFET switching loss models to resolve inaccuracies observed with conventional Si MOSFET models. EMI is then compared between SiC and Si MMC using carefully controlled relative measurements of radiated EMI.

A New SST Topology Comprising Boost Three-Level AC/DC Converters for Applications in Electric Power Distribution Systems

The growing interest in integrating distributed generation into the existing power distribution grid, the increase in the penetration levels of renewables, as well as the need to achieve a more efficient, reliable, and sustainable grid is leading to the development of new grid-interfaced power converters such as the solid-state transformer (SST). As current and voltage ratings of commercially available power semiconductor devices are normally below power ratings required in distribution systems (e.g., 13.8 kVrms), multiple modules must be connected in cascade configuration at the high-voltage (HV) side to reach higher voltage ratings as well as in parallel at the low-voltage (LV) side to achieve high current levels. A new SST topology consisting of modular boost-based three-level ac–dc converters, medium-frequency transformers with two secondary windings, and four-leg ac–dc converters is presented in this paper. When compared to similar approaches, the proposed topology comprises fewer power conversion stages, lower voltage across the semiconductor devices on the HV side, and lower current flowing through each device on the LV side. These characteristics reduce the number of series-connected modules in the HV side and parallel-connected devices in the LV side. The feasibility of the proposed topology is experimentally validated on a 500 W, 120 Vac/48 Vdc scaled-down prototype.

Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature ( ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ ) and switching energy ( ${\bm {\Delta }}{{\bm {E}}_{{\bf SW}}}$ ) between the parallel-connected devices for a given difference in the gate and thermal resistance ( ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ and ${\bm {\Delta }}{{\bm {R}}_{{\bf TH}}}$ ) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ and ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.

Evaluation of thermal performance of all-GaN power module in parallel operation

This work presents an extensive thermal characterization of a single discrete GaN high-electron-mobility transistor (HEMT) device when operated in parallel at temperatures of 25 °C–175 °C. The maximum drain current (ID max), on-resistance (RON), pinch-off voltage (VP) and peak transconductance (gm) at various chamber temperatures are measured and correlations among these parameters studied. Understanding the dependence of key transistor parameters on temperature is crucial to inhibiting the generation of hot spots and the equalization of currents in the parallel operation of HEMTs. A detailed analysis of the current imbalance between two parallel HEMT cells and its consequential effect on the junction temperature are also presented. The results from variations in the characteristics of the parallel-connected devices further verify that the thermal stability and switching behavior of these cells are balanced. Two parallel HEMT cells are operated at a safe working distance from thermal runaway to prevent destruction of the hottest cell.

Yield Prediction Method of a Reaction in a Micro-Fluid Device and Experimental Proof of Increased Production Using Parallel-Connected Devices

The yields of consecutive reactions in a micro-fluid device were predicted by using Monte Carlo simulation. It was found that the yield of main product was improved by using a micro-fluid device when the ratio of the reaction rate constants is k1/k2 >1. The yield prediction map was also made by using non-dimensional Damkohler Number Da and the ratio of the reaction-rate constants k1/k2. The validation experiments of four kinds of consecutive reactions were conducted. Next, the micro-fluid system of 20 parallel-connected micro-fluid devices was developed. The maximum flow rate of the micro-fluid system was 10 mm3/s, which corresponds to 315 t/year. Evaluation of the chemical performance of the micro-fluid system was conducted using a nitration reaction. It was found that the micro-fluid system increased the production scale without decreasing the yield of the products.

Challenges Regarding Parallel Connection of SiC JFETs

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.

Analytical model and characterization of abnormally structured MOSFETs

Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate widths. Linear resistance and saturation drain current of the devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistors. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes.