Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Abstract

Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature ( ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ ) and switching energy ( ${\bm {\Delta }}{{\bm {E}}_{{\bf SW}}}$ ) between the parallel-connected devices for a given difference in the gate and thermal resistance ( ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ and ${\bm {\Delta }}{{\bm {R}}_{{\bf TH}}}$ ) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ and ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.