Numerical study of destruction phenomena for punch-through IGBTs under unclamped inductive switching

Abstract

In this paper, a numerical description of the ruggedness of punch-through (PT) IGBTs under the unclamped inductive switching (UIS) has been proposed using two-dimensional (2D) simulations with the calibration to experimental results. The UIS capability is an important design factor of device structures for the purpose of screening defects produced during the wafer process. The local hot spot due to the current filament three-dimensionally (3D) distributed over the chip area requires 3D simulations to reproduce the current density of the filament and its behavior leading to the device destruction; however, it is difficult to simulate such a large area with an appropriate mesh size and a boundary condition. To provide a possible solution of this technical issue, 2D simulations using large scale multi-cell structures with the increased current density has been proposed to reproduce experimental results without resorting to 3D simulations. With this approach, not only destructive phenomena including the UIS ruggedness and the latch-up failure mode have been reproduced, but also the device internal state leading to the destruction has been revealed. The spatial distribution of the electric potential and the lateral electric field during the UIS condition is shown to be a key role determining the current filament width and the UIS ruggedness. Besides, the high frequency oscillation of the collector voltage during the UIS observed by experiments has been analyzed and has found to be related with the hopping motion of the current filament from a cell to its neighboring cell of the device.