Challenges Regarding Parallel Connection of SiC JFETs

Abstract

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.