Parabolic Potential Approximation Research Articles

Accurate 2-D analytical model for cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET with scaled channel length

In this article, we propose a 2D analytical-model of a cylindrical gate-junctionless ferroelectric-nanowire (CG-JFe-NW) MOSFET for evaluating central potential, electric field, threshold voltage, mobility and current voltage characteristics. Central potential, threshold voltage, and current in the linear and saturation regions are derived by solving the 2D Poisson’s equation employing the parabolic-potential- approximation (PPA) profile. The recommended model is appropriate for compact modelling as it includes the phenomenon of bulk conduction, surface conduction and ferroelectric negative capacitance in all the regions of the device operation. Ferroelectric properties are introduced by combining Silicon doped hafnium oxide (ferroelectric layer) with HfO2 and SiO2 (dielectric layers), and an extensive study has been performed to determine the effects of interfacial-layer thickness and variation of channel length on device performance. For all relevant device characteristics and for all the operational voltage ranges, it is demonstrated that the analytical model entirely corresponds with the numerical simulations. For simulations, the Atlas 3-D simulator has been taken into consideration.

Threshold voltage modeling based comparative performance exploration of Junctionless and Junction-Based High-K gate stack Dual-Material Cylindrical Gate-All-Around Macaroni MOSFET

This paper presents explicit threshold voltage modeling based comparative threshold voltage exploration of Junctionless (JL) and Junction-based (JB) High-K gate stack (HKGS) Dual-Material (DM) Cylindrical Gate-all-around (CGAA) Macaroni (Mac.) MOSFET. Based on Young’s popular Parabolic Potential Approximation (PPA), device features like inner potential has been formulated. Based on the expression of inner potential, threshold voltage has been extracted. Other major short channel effects like Drain-induced barrier lowering (DIBL) and subthreshold swing (SS) have also been analyzed. Device parameters such as inner, outer radii, channel lengths, type of high-k gate oxide, source/drain doping for JB device, etc. have also been varied to examine their effects on device parameters. Finally mathematical outputs have been corroborated with simulation outputs from Atlas.

An Analytical Approach to Study the Impact of Traps on Ge-Source Double Gate PNPN TFET

The analytical models for surface potential, electric field, and drain current of a Ge-source double gate hetero-structure PNPN Tunnel FET are developed taking into account the oxide-semiconductor interfacial trap charges. Although other researchers have used similar modeling techniques on various structures, the proposed structure has not yet utilized them when considering the source/drain depletion region and interfacial trap charges that reflect changes in the flat band voltage. The proposed device consists of Ge-source, Si1−xGex pocket (mole fraction 0.3), and Si channel and drain. Moreover, the non-uniform concentration of trap charges is considered at the oxide/semiconductor interfaces: 1013 cm−2 at HfO2/ Si1−xGex interface and 1012 cm−2 at HfO2/Si interface. 2D Poisson’s equation is solved with the help of parabolic potential approximation and different boundary conditions to develop the surface potential model. The developed potential model is subsequently used to construct the electric field model. The drain current model of the proposed TFET is finally developed with the help of the generated electric field and some other parameters. All the developed models are validated using TCAD-simulated data. The studies show that there is good agreement between the simulated and modeled results, ensuring the applicability of the device in charge-trapped memory systems based on tunneling.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

Abstract In this work, an innovative structure of a novel double gate tunnel field-effect transistor (TFET) is proposed with a channel length of 20 nm.The gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept. The device exhibits suppressed ambipolar current, excellent subthreshold swing and good ION/IOFF ratio. The proposed structure proves to be a promising candidate for high speed applications as it shows lesser gate-capacitance than conventional stacked-oxide gate structure. The surface potential and electric field have been modelled considering the depletion regions, using 2-D Poisson's equation with appropriate boundary conditions, based on parabolic potential approximation. A semi-empirical method has been utilized to incorporate the effect of mobile charges on the device characteristics. A physics-based model for charge and terminal capacitances has been derived, following the potential model. The drain current model is able to accurately predict the ambipolar current as well as the effects of drain voltage in saturation region. Proper optimization of the device structure has been performed to derive the best desired electrical characteristics. SILVACO ATLAS simulation data have been used to validate the analytical results of the proposed structure, thereby corroborating the precision of the present analytical model. Finally, an inverter circuit has been designed in CADENCE circuit-simulation environment to justify the usage of our device in low power and high speed digital circuit applications.

Probability Density, Transition Frequency and Spontaneous Emission Rate in the Asymmetric Gaussian Potential Two-Level System with Magnetic Field

The electronic probability density, the transition frequency and the longitudinal optical (LO) phonon spontaneous emission rate in the two-parameter asymmetric Gaussian (AG) potential two-level system with magnetic field are studied by using the Pekar variational method, and their single-parameter parabolic potential approximation is discussed. Numerical results show that the selecting the two-parameter AG potential to describe the restricted effects of electron in quantum dot can more accurately reveal the quantization characteristics of the wave property of electronic states, the statistical regularity of electron motion and the LO phonons’ spontaneous emission rate, and the results given by the single-parameter parabolic approximation are relatively rough. The influence of the magnetic field, dispersion and electron–phonon coupling of materials on the probability distribution, quantum transition frequency and the LO spontaneous emission rate in the two-level system cannot be ignored.

Channel Length Scaling Pattern for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

The natural length of MOSFETs helps to describe the potential distribution in the Silicon substrate. This natural length varies in different device structures, from a single gate to multi-gate device geometry. To measure the short channel effects degree, the natural length should be known because various vital parameters such as OFF-current, Roll-off threshold voltage, and drain induced barrier lowering depend on it. In this research work, authors have presented a scaling theory for Cylindrical Surrounding Double-Gate (CSDG) MOSFET, which guide the device design. The scaling method has been derived, based on the application of the Poisson equation, in a cylindrical structure using Parabolic Potential Approximation (PPA) along the radial direction (substrate part only). Furthermore, a comparison with cylindrical surrounding-gate MOSFETs, Silicon-on-insulator, and double-gate device geometries has been obtained. The results obtained using the PPA model show that CSDG MOSFET has the least natural length, making it a better component for SCEs immunity.

3-D Analytical Modeling of Triple Metal Tri-Gate Graded Channel High-k SON TFET for Improved Performance

In this paper, three dimensional analytical paradigm for triple metal graded channel high-k silicon-on-nothing tunnel field effect transistor (TM-TG GC-High-k SON TFET) is deduced in terms of surface potential, electric field and drain current parameters. 3-D Poisson’s equation and Kane’s model are solved considering popular parabolic surface potential approximation technique along with assuming suitable boundary conditions for deriving the aforementioned electrical characteristics of the device under consideration for evaluation of its short-channel performance. It is demonstrated that the proposed structure offers sharp band bending phenomenon at source-channel interface with application of appropriate gate bias to revamp the drive current. At the same time, it results larger tunneling width at the channel-drain interface to subdue the possibility of reverse tunneling as compared to other reported structures. The results predicted by the model are compared with simulation data to verify the exactness of the developed analytical model. Further, the device is optimized in respect of selecting metal work function values and corresponding gate lengths along with adopting proper gate-stack combination (choice of high-k with SiO2) for enhanced performance.

Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects

In this paper, an analytical threshold voltage model of double gate-all-around metal-oxide-semiconductorfield-effect-transistors (DGAA MOSFETs) including the fringing field effects is developed. The total fringing capacitance arising due to induced fringing fields in the device is divided into inner, outer and bottom fringing capacitance. A simple expression for each fringe capacitance is developed individually. The 3-D Poisson's equation has been solved in the channel region using the parabolic potential approximation method to develop the surface potential expressions. The effects of fringing capacitances of inner and outer gates which causes charge induction in the source/drain regions have been incorporated within the developed surface potential expressions. The change in potential due to these induced charges of source/drain region along the channel is formulated and added with the developed surface potential expression at both surfaces. The obtained modified surface potential equations have been utilized to derive the expression of the threshold voltage of the device. The performance of the proposed model has been compared with the previously developed model of DGAA MOSFET structure without High-k dielectrics. The effects of variation of device parameters on the threshold voltage have been also analyzed. The accuracy of the proposed model has been verified by numerical simulation results obtained by a device simulator VTCAD from Cogenda Int.

Explicit continuous models of drain current, terminal charges and intrinsic capacitance for a long-channel junctionless nanowire transistor

An explicit charge-based solution for the drain current, terminal charges and intrinsic capacitance of a long-channel junctionless nanowire transistor (JNT) incorporating the importance of an interface trap density that affect the threshold voltage and the subthreshold slope is presented in this study. Initially, a continuous implicit solution of the unified charge-based control model (UCCM) is derived from the 1D Poisson equation by invoking the parabolic potential approximation. The the continuous solution of the mobile charge density at the source/drain is obtained by adding the decoupled UCCM expression for the depletion and complementary parts, where each part is explicitly solved using the Lambert function without having an additional smoothing function to unify the two limits. The omission of an additional smoothing function could lead to a shorter computation time. Secondly, by solving Pao-Sah’s dual integral, a continuous charge-based expression for the drain current is derived. The expressions for the terminal charge are then derived based on the decoupled drain current model that also becomes an input for computing all four independent capacitances of the JNT. The explicit continuous models show a good agreement with numerical simulation over practical terminal voltages, doping levels, and geometry effects. For a given maximum surface potential error of 5%, the model is accurate for a dopant-geometry ratio of 0.001 < qNDR2/4ϵSi < 0.3 and it is also independent of fitting parameters that may vary for different terminal biases or dopant geometries. The nonpiecewise models for drain current, terminal charges and intrinsic capacitance are significantly resolved by decoupling the mobile charge into depletion and complementary parts with no additional smoothing function to unify between operating regions, and omitting fitting parameters that have no physical meaning.

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.

Modeling and Analysis of a Front High-k gate stack Dual-Material Tri-gate Schottky Barrier Silicon-on-Insulator MOSFET with a Dual-Material Bottom Gate

The present work centralizes the analytical modeling of a novel structure namely front high-k gate stack Dual-Material Tri-gate Silicon-on-insulator Schottky barrier MOSFET with a dual material bottom gate along with an emphasis on its response towards the various SCEs. 3-D Poisson’s equation along with proper boundary conditions has been solved considering the popular parabolic potential approximation. Different device features like surface potential, threshold voltage, electric field has been studied. Also the device immunity towards the several Short channel effects like drain-induced barrier lowering, threshold voltage roll-off, hot carrier effects are investigated minutely. The analytical results obtained have been verified using simulation results obtained from ATLAS.

Analytical modelling and performance analysis of gate engineered TG silicon‐on‐nothing metal–oxide–semiconductor field‐effect transistor

This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

On the influence of scattering on atomic strings on the stability of planar channeling of high-energy positively charged particles

The problem of the stability of planar channeling of high-energy positively charged particles in a crystal was studied on the basis of analytical calculation and numerical simulation. The evolution of the spectral density of radiation of particles with a decrease of the angle between particle momentum and atomic strings was investigated. The frequency of the peak in radiation, that corresponds to scattering by individual atomic strings in the case of planar channeling, was found. The analytical calculation was carried out in the parabolic planar potential approximation, while in the numerical simulation the Doyle-Turner approximation was used.

2-D modeling and analysis of short-channel behavior of a front high-K gate stack triple-material gate SB SON MOSFET

This paper presents the 2-D analytical modeling of a front high-K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson’s equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

Two dimensional analytical modeling of a high-K gate stack triple-material double gate strained silicon-on-nothing MOSFET with a vertical Gaussian doping

This paper presents the two-dimensional analytical modeling of high-k gate stack Triple material double gatestrained SON MOSFET with a vertical Gaussian-like doping profile. The expression for surface potential has been calculated by solving the 2-D Poisson’s equation and by considering the parabolic potential approximation. The threshold voltages as well as the electric field are also calculated for the proposed model. In addition, detailed studies of the device response towards the various short-channel effects are also examined. The analytical results are verified using the results obtained from a 2-D device simulator, namely ATLAS, Silvaco.

A Threshold Voltage Model of Silicon-Nanotube-Based Ultrathin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects

In this paper, a quantum-mechanical threshold voltage model for ultrathin double gate-all-around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's and 2-D Schrodinger's equations in the channel region. The parabolic potential approximation is considered for Poisson's equation solution, whereas a hollow cylindrical potential well in the channel region is assumed to solve Schrodinger's equation. Simple equations for the wave function and energy quantization in the channel of DGAA MOSFET have been formulated. Discretized energy levels have been used for channel charge calculation in subthreshold regime of device operation. The calculated channel charge is compared with a threshold charge to formulate the threshold voltage model. The effects of the device parameters such as the channel thickness, oxide thickness, doping, etc. on threshold voltage and DIBL have been extensively studied. The proposed model results have been verified by comparing with the numerical simulation results obtained from the 3-D device simulator Visual TCAD of Cogenda Int.

Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poisson's equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.

Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors

In this work, the negative capacitance phenomenon exhibited by ferroelectric materials has been incorporated in Junctionless Cylindrical Surrounding Gate (JLCSG) transistor and an analytical model has been developed to study the electrical characteristics of the device by taking into account Landau Khalatnikov equation along with parabolic potential approximation. Using the derived model various electrical parameters such as potential, gain, drain current, gate capacitance etc have been obtained. Silicon doped hafnium oxide has been incorporated as the ferroelectric material and exhaustive study has been done to study the impact of interfacial layer and metal workfunction on device characteristics as these have significant impact on the performance of Junctionless devices. It has been demonstrated by analytical model and TCAD simulations that by incorporating ferroelectric layer and optimizing metal work function and interfacial layer thickness, the device performance of JLCSG can be substantially improved.

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

3-D Analytical Modeling of Dual-Material Triple-Gate Silicon-on-Nothing MOSFET

A 3-D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET is proposed in this paper. 3-D Poisson’s equation with proper boundary conditions was solved to obtain the surface potential variation of the structure considering the popular parabolic potential approximation, and the threshold voltage and electric field were calculated for the model. The proposed model’s immunity to the various short-channel effects, such as threshold voltage roll-off, Drain-Induced Barrier Lowering (DIBL), and subthreshold swing, are also examined, and the impact of the various device parameters on the performance of the device is studied. The 3-D simulated results obtained using ATLAS, a device simulator from Silvaco, validate the analytical results obtained for this structure.