Package Substrate Research Articles

Morphology Evaluation of Microelectronic Packaging Substrates Using Shadow Moiré Technique

The surface quality and long-term reliability of packaging substrates in microelectronic packaging processes have become subjects of increasing concern as circuit board component density increases while the pitches of these components decrease. As a result, packaging substrate morphology inspection is becoming more crucial than ever before. This paper presents a noncontact measurement technology based on a shadow moire technique to evaluate the surface quality and morphology of microelectronic packaging substrates. Fringe pattern images of packaging substrates are acquired through the noncontact measurement technology, and the resulting images are then analyzed using the phase-shifting technique to determine the morphology and surface quality (specifically, the flatness) of the microelectronic packaging substrates. A full-field morphology measurement system with adjustable sensitivity and measurement range was developed. The measurement system was tested using three typical types of microelectronic packaging substrate, a coin and a step made from two standard gauge blocks. The measurement system proved to be both feasible and effective by the test results.

In-situ Residual Stress Analysis of Semiconductor Packaging Substrate Resins in Thermosetting Process for Investigation of their Optimum Manufacturing Process

In-situ Residual Stress Analysis of Semiconductor Packaging Substrate Resins in Thermosetting Process for Investigation of their Optimum Manufacturing Process

System Scaling With Nanostructured Power and RF Components

The emergence of smartphones and other smart systems is driving new trends in electronics scaling that goes beyond transistors or active devices, to include all the system components such as packaging substrates, passive components, thermal structures, power sources, and the system interconnections. Current system components are at milliscale, creating a $10^{3}$ to $10^{6}$ scaling gap with the packaging interfaces at microscale, and transistors at nanodimensions. With current microstructured materials, component miniaturization also degrades performance metrics such as efficiency, tolerance or precision, thermal and frequency stability. Nanostructured materials and processes can potentially miniaturize these system components, while simultaneously enhancing the performance. These nanostructured components are assembled close to the active devices, resulting in ultraminiaturized and ultrathin systems with 3-D integration of passives with actives. This paper shows the impact of nanostructured materials toward enhancing the performance and miniaturization of power and radio-frequency (RF) passive components in emerging smart systems. Opportunities for nanostructured materials in improving the power density and efficiency of capacitors and inductors in power-supply modules are reviewed in the first part of the paper. The impact of nanostructured magnetic, dielectric and magneto-dielectric films on emerging RF subsystems is illustrated in the last part of the paper.

Quasi-Lumped-Element Filter Based on Substrate-Integrated Suspended Line Technology

Quasi-lumped-element low-pass filter (LPF) and high-pass filter (HPF) based on substrate-integrated suspended line (SISL) technology are presented in this paper. Double interdigital capacitor, which has advantages of high capacitance density and high quality factor, is analyzed and designed to minimize the filter size. Based on the theoretical analysis, quasi-lumped-element SISL LPF and HPF prototypes are designed. The experimental results show that the SISL LPF achieves ultra-wide stopband up to 24 $\text{f}_{c}$ ( $\text{f}_{c}$ is the cut-off frequency) with compact size of $0.180~\lambda _{g} \times 0.082~\lambda _{g}$ ( $\lambda _{g}$ is the guide wavelength at $\text{f}_{c})$ . The SISL HPF features the low insertion loss of only 0.3 dB, while the size is only $0.108~\lambda _{g} \times 0.085~\lambda _{g}$ . Moreover, the methods of substrate excavation and packaging optimization are proposed to further enhance the performance of SISL LPF and SISL HPF. By doing so, the stopband of SISL LPF is further extended to 32 fc, and the insertion loss of SISL HPF is significantly reduced to 0.1 dB.

Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling

Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure–material–assembly–reliability–thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.

Strain transferring mechanism analysis of the substrate-bonded FBG sensor

One of the important application forms of Fiber Bragg grating (FBG) is to measure strain by pasting on the surface of structure. In order to improve the strength of surface-bonding FBG, packaging substrate in metal slice is designed and applied. On the basis of previous studies, an analytic model of the substrate-bonded FBG sensor is developed to predict the strain transfer rate. Moreover, the effects of substrate material and sizes on the strain transfer rate of substrate-bonded FBG are analyzed and compared. Finally, the theoretical analysis results are verified by experimental results. There is a good correspondence between the calculated values and experimental results.

Modeling Vibration Induced Fatigue Failure of Free Standing Wire Bonds

Abstract Wire bonds are used to connect device terminals to package terminals or substrate terminal that forms circuits that are needed to create desired higher level functions. If a wire bond breaks or becomes detached during operation, the desired function will be lost. Depending on the design, a loss in function could be catastrophic. Aluminum, gold, and copper wires are used to create wire bonds in electronic products. These materials have been selected for their ability to be formed as fine wires and their ability to provide low electrical resistance. In many electronics packages, wire bonds are encapsulated in a polymer molding compound that is used to protect the electronic device. However, in some electronic devices such as hermetically sealed cavity packages, wire bonds may be free-standing. Under vibration loading, free-standing wire bonds may be subject to failure due to mechanical fatigue. In this work, an analytic model is presented for predicting natural frequency of a free-standing wire bond and for assessing a wire bond time to failure under a harmonic loading condition. The model for natural frequency is calibrated by finite element analysis and validated through experimental testing. The life prediction model, a test plan, and preliminary test results are presented.

Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging

Abstract This paper outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully-printed, highly-integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an IC die are presented using printed dielectric ramps and coplanar waveguide (CPW) transmission lines exhibiting low loss (0.6–0.8 dB/mm at 40 GHz). Stereolithography (SLA) 3D printing is presented for the encapsulation of IC dies, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface (FSS)-based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulation, or through-mold vias (TMVs), achieving a slope up to 65° and low loss (0.5–0.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages.

Chip-Scale Near-Field Resonant Power Transfer via Elastic Waves

This paper reports on the proof-of-concept demonstration of an approach for the synthesis of a through package charging and authenticating communication link enabled by GHz-range aluminum nitride (AlN) piezoelectric transducers. The acoustic link is formed by two thickness-mode acoustic transducers placed on the two sides of a packaging substrate. The link leverages the enhancement of energy transfer that occurs at resonance; 1- $\mu \text{m}$ -thick (2.7 GHz) and 6- $\mu \text{m}$ -thick (500 MHz) AlN acoustic links are demonstrated showing substantial enhancement of power transfer efficiencies (PTE) when using thicker AlN substrates. PTEs of −8 dB at 2.7 GHz and −2 dB at 500 MHz are measured for transducers’ size of $1\times 100\times 100~\mu \text{m}^{3}$ and $6\times 100\times 100~\mu \text{m}^{3}$ through 700- and 500- $\mu \text{m}$ -thick silicon substrates, respectively. The experimental values are in very close agreement with the analytical model of the acoustic link. The potential misalignment between the two transducers is the main limitation of this approach. To overcome this challenge, acoustic phased arrays are devised to enable steering of the transmitted beam. Preliminary results on the steering capability demonstrate about 8 dB of improvement in PTE via a two-element array when dealing with a 100- $\mu \text{m}$ misalignment. This paper is the first step toward the development of next-generation high-efficiency and micro-scale power transfer units that could energize chips through packages. [2017-0010]

Preparation and properties of antioxidative BaO–B2O3–SiO2 glass-coated Cu powder for copper conductive film on LTCC substrate

In this study, uniform BaO–B2O3–SiO2 glass coatings on micro Cu powders with different glass/Cu ratio were prepared by sol–gel method. The pastes prepared with the glass-coated Cu powders were screen printed on low temperature co-fired ceramic (LTCC) substrate. Then the dry films on substrate were binder-burned-out at 400 °C in air and co-fired at 910 °C in N2 atmosphere. During the binder-burning-out process, the oxidization of the films with 9 and 11 wt% glass was slight because of the improvement of oxidization resistance of the glass-coated Cu powders. Moreover, the sintered film with 9 wt% glass coating showed no crystal phase of copper oxide and had small sheet resistance of 1.3 mΩ/□, which can be used as good conductive thick film on LTCC substrate for microelectronic packaging.

Photodeprotectable N-Alkoxybenzyl Aromatic Polyamides.

N-alkoxybenzyl aromatic polyamides were synthesized by polycondensation of N-alkoxybenzyl aromatic diamine with equimolar dicarboxylic acid chloride in the presence of 2.2 equiv. of pyridine at room temperature for 2 days. The obtained polyamides were mainly cyclic polymers, as determined by means of matrix-assisted laser desorption ionization time-of-flight (MALDI-TOF) mass spectrometry, and showed higher solubility in organic solvents than unprotected aromatic polyamides. Photodeprotection of N-alkoxybenzyl aromatic polyamide film containing photo acid generator (PAG) proceeded well under UV irradiation (5 J/cm2), followed by heating at 130 °C for 15 min. The nature of the polymer end groups of N-alkoxybenzyl aromatic polyamides was found to be crucial for photodeprotection reactivity. These polymers are promising candidates for photosensitive heat-resistant materials for fine Cu wiring formation by electroless Cu plating of high-density semiconductor packaging substrates.

Effect of anisotropic thermo-elastic properties of woven-fabric laminates on diagonal warpage of thin package substrates

Warpage of thin package substrates and their in-plane orientation at room temperature were studied, focusing on the thermo-elastic properties of woven-fabric (WF)/epoxy laminates. It was recently observed that most of the severe warpage of thin package substrates fabricated from WF laminates was diagonal, which lowers significantly the yields of various processes. The final strip warpage primarily originates from residual stress of the first base substrate, a copper clad laminate (CCL). Therefore, we investigated the built-in residual stress, which develops during the thermo-compression bonding of the CCL. For this study, CCL specimens with 100–150μm thick WF laminates were prepared in order to understand the warpage mechanism. Flexural moduli and coefficients of thermal expansion (CTE) of the composite substrates were accurately measured in four orientations (0, 45, 90, 135)° to correlate with the warpage orientation using a three-point bending test and digital image correlation method, respectively. The mechanism that determines warpage orientation was verified using finite element simulation, indicating the importance of considering both orthotropic elastic modulus and anisotropic CTE with a non-zero shear CTE of the thin WF laminate in warpage analysis.

Evaluation of current and temperature effects on optical performance of InGaAlP thin-film SMD LED mounted on different substrate packages

The relationship between the photometric, electric, and thermal parameters of light-emitting diodes (LEDs) is important for optimizing the LED illumination design. Indium gallium aluminium phosphide (InGaAlP)-based thin-film surface-mounted device (SMD) LEDs have attracted wide attention in research and development due to their portability and miniaturization. We report the optical characterization of InGaAlP thin-film SMD LED mounted on FR4, 2 W, and 5 W aluminum (Al) packages. The optical and thermal parameters of LED are determined at different injection currents and ambient temperatures by combining the T3ster (thermal transient tester) and TeraLED (thermal and radiometric characterization of power LEDs) systems. Analysis shows that LED on a 5 W Al substrate package obtains the highest luminous and optical efficiency.

Fabrication and microwave dielectric properties of CuO-B 2 O 3 -Li 2 O glass-ceramic with ultra-low sintering temperature

Abstract CuO-B 2 O 3 -Li 2 O (CBL) glass-ceramic with a composition of 32 wt% CuO − 63 wt% B 2 O 3 − 5 wt% Li 2 O was prepared through conventional glass-ceramic route. The CBL glass-ceramic could be densified well by sintering at 625 °C for 30 min. The X-Ray diffraction (XRD) and transmission electron microscopy (TEM) analysis indicated that the CuB 2 O 4 phase was dominated in the sintered glass-ceramic, which showed excellent microwave dielectric properties with e r = 5.84, Q × f = 10120 GHz (at 13.44 GHz), and τ f = −33 ppm/°C. Furthermore, the CBL material is chemically compatible with both silver (Ag) and aluminum (Al) electrodes at their sintering temperatures. These properties indicate that the CBL glass-ceramic might be a promising ultra-low temperature co-fired ceramic (ULTCC) material for packaging substrate applications.

(Gordon E. Moore Medal for Outstanding Achievement in Solid State Science and Technology Address) Transient Polymers for Low-k Dielectrics and Vaporizing Devices

Dielectric materials provide critical functions throughout the interconnect hierarchy, including on-chip dielectrics, package substrates, and printed wiring boards. Transient polymers, those which vaporize on command, can be used to form ultra low-k dielectrics, such as porous materials or air-cavities. Transient polymers can also be used as coatings or structural materials in electronic packages and devices enabling the disappearance of the device when the collection, recovery or disposal of the device is difficult. In this presentation, the motivation and opportunity for improved electronic materials will be presented. The nature of transient polymers will be described including their synthesis, physical properties, and chemical reactivity. Transient polymers can be decomposed into liquids or gases when exposed to a thermal, chemical or photo-chemical stimulus. Finally, several applications for transient polymers in the fabrication of unique electronic devices, structures or packages will be described.

Physical and Functional Characterization of a Viral Genome Maturation Complex

Genome packaging is strongly conserved in the complex double-stranded DNA viruses, including the herpesviruses and many bacteriophages. In these cases, viral DNA is packaged into a procapsid shell by a terminase enzyme. The packaging substrate is typically a concatemer composed of multiple genomes linked in a head-to-tail fashion, and terminase enzymes perform two essential functions: 1) excision of a unit length genome from the concatemer (genome maturation) and 2) translocation of the duplex into a procapsid (genome packaging). While the packaging motors have been described in some detail, the maturation complexes remain ill characterized. Here we describe the assembly, physical characteristics, and catalytic activity of the λ-genome maturation complex. The λ-terminase protomer is composed of one large catalytic subunit tightly associated with two DNA recognition subunits. The isolated protomer binds DNA weakly and does not discriminate between nonspecific DNA and duplexes that contain the packaging initiation sequence, cos. The Escherichia coli integration host factor protein (IHF) is required for efficient λ-development in vivo and a specific IHF recognition sequence is found within cos. We show that IHF and the terminase protomer cooperatively assemble at the cos site and that the small terminase subunit plays the dominant role in complex assembly. Analytical ultracentrifugation analysis reveals that the maturation complex is composed of four protomers and one IHF heterodimer bound at the cos site. Tetramer assembly activates the cos-cleavage nuclease activity of the enzyme, which matures the genome end in preparation for packaging. The stoichiometry and catalytic activity of the complex is reminiscent of the type IIE and IIF restriction endonucleases and the two systems may share mechanistic features. This study, to our knowledge, provides our first detailed glimpse into the structural and functional features of a viral genome maturation complex, an essential intermediate in the development of complex dsDNA viruses.

Guest Editors’ Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory

While CMOS scaling definitely has a few more technology nodes to go, the end of its roadmap comes into sight, if only for reasons of economic viability. Semiconductor companies are seeking alternatives to provide the increased functionality and performance under constrained power and financial budgets their customers have grown accustomed to. An emerging solution is vertical (3-D) stacking of various dies as a single packaged chip product. Strictly speaking, 3-D stacking has already started several decades ago with multichip modules (MCMs), package-on-package (POP), and system-in-package (SIP). However, in these products, the die-to-die communication has been handled via interconnects that run via the package substrate and hence qualify as “off-chip,” i.e., relatively slow and power hungry.

Development of Fan Out Package Platform for High Performance and RF Applications

ABSTRACT Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors. In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

Analysis of Spatial Inhomogeneity of Residual Stress at Interface between Substrate Resins and Copper Foils in Semiconductor Packaging Substrates

Analysis of Spatial Inhomogeneity of Residual Stress at Interface between Substrate Resins and Copper Foils in Semiconductor Packaging Substrates

In situ Residual Stress Analysis in Thermosetting Resins for Semiconductor Packaging Substrate during Curing Process for Investigation of their Optimum Thermal Process

In situ Residual Stress Analysis in Thermosetting Resins for Semiconductor Packaging Substrate during Curing Process for Investigation of their Optimum Thermal Process