Abstract
While CMOS scaling definitely has a few more technology nodes to go, the end of its roadmap comes into sight, if only for reasons of economic viability. Semiconductor companies are seeking alternatives to provide the increased functionality and performance under constrained power and financial budgets their customers have grown accustomed to. An emerging solution is vertical (3-D) stacking of various dies as a single packaged chip product. Strictly speaking, 3-D stacking has already started several decades ago with multichip modules (MCMs), package-on-package (POP), and system-in-package (SIP). However, in these products, the die-to-die communication has been handled via interconnects that run via the package substrate and hence qualify as “off-chip,” i.e., relatively slow and power hungry.
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