P-type Wafers Research Articles

Light-emitting porous silicon: a structural investigation by high spatial resolution Raman spectroscopy

The structure of light-emitting porous silicon layers, prepared by anodization of p-type wafers, has been investigated as a function of depth by microprobe Raman spectroscopy. The depth-profiles of the Raman scattering from aged samples, several micrometres thick, were carried out in the region of the optical phonons for crystalline silicon. The Raman data indicate the presence of both a predominant nanocrystalline phase and of an amorphous silicon component at any depth within the porous layers. A quantitative analysis of the experimental spectra is carried out in the frame of phonon confinement models, by assuming both a spherical shape for the nanocrystals and an inhomogeneous distribution of their sizes. When the probing laser spot approaches the region near the interface with vacuum, a remarkable reduction of the average size of the nanocrystals is found, with a substantially unchanged a-Si component.

An in-depth analysis of the 'Elymat' technique for characterizing metallic microcontamination in silicon: Experimental validation for iron contamination in p-type wafers

Application of the on-line Elymat technique for measuring bulk carrier recombination lifetime is numerically analysed using a complete three-dimensional carrier transport simulation including the Dember electric field, the characteristics of the laser beam, the transport parameters of the wafer and Shockley-Read-Hall recombination kinetics. We found a strong dependency of the measured lifetime on the shape and power of the laser beam as well as on the deep energy level of the impurity in the gap, owing to nonlinear effects not described by the classical model. Our numerical simulations show that the use of a small laser beam permitting the approximation of point-like excitation gives the most reliable results. The comparison between our numerical simulations and experimental results for iron-contaminated p-type samples with a resistivity between 1 and 18 Omega cm shows that the donor level of Fe-B pairs at Ec-0.3 eV and not the classical acceptor level at Ev+0.1 eV is the predominant site of recombination of Fe-B pairs in p-type silicon in the above doping range. First results for the electron and hole capture cross sections for this defect will be given. Based on these results, the sensitivity of the technique is shown to be less than 1011cm-3 in the case of Fe-B pairs corresponding to less than 10 PPT (parts per trillion).

Observation of hydrogen in commercial Czochralski-grown silicon wafers

Commercially available, Czochralski-grown (CZ), phosphorus- and boron-doped (100) silicon wafers have been characterized by capacitance-voltage and deep-level transient spectroscopy measurements of Schottky diodes. Two electron traps labelled A1 (Ec-0.10 eV) and A2 (Ec-0.13 eV) are commonly observed in n-type wafers with a concentration around 1011 cm-3. These correspond to the hydrogen-related complexes previously reported. A decrease of carrier concentration occurs near the surface in p-type wafers. This is ascribed to the passivation of boron acceptors by hydrogen. These results indicate that hydrogen is incorporated near the surface in commercial CZ silicon wafers.

Some preliminary observations of the rapid thermal oxidation of porous silicon, and the rapid thermal nitriding of oxidized porous silicon

Porous silicon, produced by the anodic oxidation of p-type single crystal wafers of silicon in hydrofluoric acid/ethanol electrolytes has been subjected to rapid thermal oxidation. For comparison purposes, and also to generate porous oxide for subsequent nitriding, other samples of porous silicon were subjected to conventional furnace oxidation. By TEM, EDS, and ESCA it was shown that the structures and compositions of the oxides produced by the two routes were similar. It was further demonstrated that oxidized porous silicon could be nitrided by rapid thermal processing. The resulting structure, although still porous, showed a much diminished etching rate in hydrofluoric acid, compared to the original oxide.

Evidence of a shallow junction formation from plasma enhanced chemical vapor deposition of boron nitride and silicon boron nitride

Dielectric constant characterization of plasma-enhanced chemical vapor deposition (PECVD) of boron nitride (BN) and silicon boron nitride (SiBN) films is studied using metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM) structures. Using the measurement technique of calculating the dielectric constant value from the capacitance, the average dielectric constant value for the BN and SiBN films deposited under similar conditions can vary as much as 40% (from 2.8 to 4.4). Low dielectric constant values are normally observed on MIS structures where the silicon substrate is n-type. Detailed C-V analysis at various test frequencies (100 Hz–1 MHz) shows that the flatband and the threshold voltages shift more than 30 V in n-type and p-type substrate wafers, respectively. These C-V characteristics suggest the formation of a junction at the insulator-substrate interface. This interface junction is probably formed by the boron-rich nitride deposition during the transient period and subsequent boron diffusion to the silicon substrate. Accounting for this p-n junction on n-type substrate wafers, the adjusted dielectric constant for MIS structures on n-type substrate is between 4 and 5, which is the same for MIS structures on p-type substrate and MIM structures.

可視発光多孔質シリコンの微細構造と結晶性

Porous silicon (hereafter PS) is produced by anodizing a silicon wafer in an HF solution. This paper describes characteristics of PS such as pore-morphology and crystallinity. Pore-morphology and crystallinity depend on anodization conditions as well as doped impurity and electrical resistivity (p) of wafers. When p-type wafers are employed, PS formed on them gives better crystallinity for lower electrical resistivity (p 1Ωcm) . The pore size of the former PS is larger than that of the latter. PS formed on n-type wafers (p<1Ωcm) consists of three layers showing different morphology depending on reaction time. Strong visible light seems to be emitted from PS composed of fine silicon crystallites with degraded crystallinity.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Luminescence Activation of Porous Silicon by Post-Anodization Treatment

ABSTRACTWe prepare “nonluminescing” porous Si by electrochemical etching (50 mA/cm2 in 50% HF diluted 1:1 with ethanol) of 1 Ω(100) p-type wafers in the absence of light in order to study the subsequent luminescence activation by postprocessing. The treatments are: photochemical etching, ageing under ambient conditions, thermal oxidation. The study reveals remarkable inhomogeneities in the depth distribution of the luminescence and allows us to comment on the relative importance of particle size, spin density and chemical composition for the luminescence.

The Effect of Lewis Base Chemisorption on the Luminscence of Porous Silicon

ABSTRACTWe report here studies on the effects of Lewis base addition on the observed luminescence of porous silicon generated non-anodically from a stain etch of &lt;100&gt; p-type wafers and whose surface morphology has been characterized by atomic force microscopy (AFM). Addition of dilute heptane solutions of alkyl amines such as n-butyl amine (C4H7NH2) results in dramatic quenching of the steady-state photoluminescence (PL) near 625 nm. The observed fractional changes in integrated PL intensity as a function of amine concentration have been fit to a simple equilibrium model demonstrating Langmuir-type behavior from which adduct formation constants have been calculated. These steady-state PL measurements are complemented by Fourier Transform Infrared (FT IR) spectroscopic measurements monitoring the effect of amine adsorption on the silicon hydride stretching modes [v(Si-Hx)] near 2100 cm-1. Based on these results, a physical model for the amine interactions with the porous silicon surface is presented.

High-Current and Low Acceleration Voltage Arsenic Ion Implanted Polysilicon-Gate and Source-Drain Electrode Si MOS Transistor

ABSTRACTThe fabrication process of high current arsenic (As) ion implanted poly-silicon (Si) gate and source-drain (SD) electrode Si n-channel metal-oxide-semiconductor field-effect-transistor (MOSFET) was examined. Poly-Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose-As implanted poly-Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique. the n-channel poly-Si gate (ps=∼L00ft/o) enhancement MOSFETs(ps-source-drain = =50n/o, SiO2 gate=380A) with off-leak-less were obtained on 3”Czochralski-grown 2Ωcm boron-doped p-type wafers (Osaka titanium). By the same process, a 8-bit single chip μ-processor with 26MHz full operation was performed.

Confirmation of Aluminum-Induced Negative Charge in Native Silicon Dioxide

Ac surface photovoltage (SPV) disappears in p-type silicon (Si) wafers rinsed with an aluminum (Al)-contaminated RCA solution, while high ac SPV appears in n-type Si wafers. This is because large negative charge due to the metal impurity causes an accumulation region at the p-type wafer surface. The negative charge vanishes with the removal of the oxide. This means that Al resides in the native oxide.

Tensile strength characterization of low-temperature fusion-bonded silicon wafers

Silicon fusion bonding was investigated with emphasis on the low temperature regime. For (100) p-type wafers with and without thermally oxidized surfaces the optimum process conditions with respect to surface preparation and gas ambient were established. H2SO4/H2O2 and hot HNO3 were found to be best suited for bonding blank/blank (without thermal oxide) and oxidized wafers, respectively. Direct measurements of bond tensile strength were made on a computer-controlled test machine. The temperature and time dependence of the bond tensile strength was determined. If the best possible clean-room conditions during processing are observed, wafers without thermal oxide, i.e. with only a chemical oxide of 25 AA thickness due to surface preparation, exhibit a measured bond tensile strength in excess of 240 kp cm-2 at a bonding temperature of only 200 degrees C and a bonding time of 4 h. This value cannot be improved by increasing the bonding temperature. If one or both surfaces are thermally oxidized the bond tensile strength is only 20% of this value. Bond tensile strength for oxidized surfaces, however, can be improved at higher temperatures to reach the high values as found for blank wafers.

Comparison of the properties of TiSi 2 films obtained by silicon and titanium co-sputtering and by composite target sputtering

Titanium disilicide films were deposited by sputtering from a sintered target or from two targets (titanium and silicon) on both n- and p-type wafers. These films were annealed using rapid thermal annealing and were analyzed using several analytical methods including Rutherford backscattering spectrometry, secondary ion mass spectrometry, X-ray diffraction and transmission electron microscopy. Targets with different residual impurity percentages have been used. Results show that the film properties are affected not only by the elaboration process but also by the initial quality of the targets. The layers obtained by co-sputtering have a resistivity as low as 13 μΩ cm and are formed with grain size of more than 1 μm.

Improvement of CMOS latch-up immunity using a high energy implanted buried layer

In this CMOS latch-up study, we compared the dc latch-up properties of devices fabricated in a p-type non-epi wafer with a high energy implanted buried p + layer to those fabricated in a p-type epi layer over heavily boron doped p + substrate. A p-type non-epi wafer with an implanted buried p + layer was found to be more effective than a p/p + epi wafer in reducing substrate resistance. The implanted non-epi wafer showed a factor of 8 improvement over the epi wafer in the NPN induced latch-up immunity. No significant device degradation was observed for devices fabracated on high energy implanted wafers.

Thermoelectric properties of boron phosphide

This paper describes the thermoelectric properties of boron phosphide wafers prepared using chemical vapour deposition and the thermal constants of a sintered boron phosphide specimen prepared using the r.f. hot pressing technique. The electric conductivity of the n-type boron phosphide wafers increases with temperature, becomes constant and then begins to decrease with temperature. In p-type wafers the conductivity increases with temperature and with a further increase in temperature the intrinsic conduction region is reached. The absolute thermoelectric power of n-type materials has an almost constant value of 500 μV K −1, but it begins to decrease at a temperature of 650 K owing to the creation of acceptors. The thermoelectric power of p-type materials decreases with increasing temperature, indicating that acceptors and donors contribute to the conduction. Thermal constants were obtained by the laser flash method and were measured using sintered discs as standards. Thermal diffusivity, heat capacity and the corresponding calculated thermal conductivity have an accuracy within ± 5% up to 700 °C. The calculated thermoelectric figure of merit is of the order of 10 −4 K −1. Therefore, boron phosphide is a promising material for high temperature thermoelectric devices.

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multiple-zone single-mask junction termination extension—A high-yield near-ideal breakdown voltage technology

The junction termination extension (JTE) technique of Temple is investigated in detail by computer simulation and experimentally. A multiple-zone JTE can be fabricated with a well-controlled single ion-implantation through a single mask with laterally variable transparencies. Analog I-V trace records of over 40 000 samples were obtained for analysis. By grouping 49 JTE designs onto region of the wafer, the effects of the JTE variations and the material variations are separated. The JTE performance agrees well with the computer results. The multiple-zone JTE of sufficient extension size achieves an essentially ideal breakdown voltage unaffected by even a factor of two in ion-implant dose variations. The JTE performs well on both n- and p-type wafers. A best design has been applied to several lots of power devices, and a yield of 99.5 percent having breakdown-voltage values within 10 percent of the ideal has been obtained. The single-mask technique assures the producibility of this 100-percent guard JTE technology, which consumes only 30 percent of the extension area needed by field rings that, at best, produced about 70 percent of the ideal breakdown voltage.

Semi-automatic, volume production of silicon solar cells

A low-cost, high-yield technology for producing single-crystal silicon solar cells at high volumes, and suitable for export to developing countries, is described. The process begins with 100 mm diameter as-sawn single-crystal p-type wafers with one primary flat. Processing steps include etching and surface texturization, gaseous-source diffusion, plasma etching, and contacting via screen printing. The necessary adaptations of such standard processes as diffusion and plasma etching to solar-cell production are detailed. New process developments include a high-throughput surface-texturization technique, and automatic printing and firing of cell contacts.The technology, coupled with automated equipment developed specifically for the purpose, results in solar cells with an average efficiency greater than 12%, a yield exceeding 95%, a tight statistical spread on parameters, and a wide tolerance to starting substrates (including the first 100 mm diameter wafers made in Canada). It is shown that with minor modifications, the present single shift 500 kWp (kilowatt peak) per year capacity technology can be readily expanded to 1 MWp per year, adapted to square and polycrystalline substrates, and efficiencies increased above 13%.

Defect-state generation in Czochralski-grown (100) silicon rapidly annealed with incoherent light

Defect-state generation in Czochralski-grown (100) silicon after rapid thermal annealing has been studied. Deep-level transient spectroscopy experiments have been carried out using Schottky barriers made on n- or p-type as-grown wafers after irradiation with a commercially available incoherent light annealing device. Neither electrical degradation nor electron-trap generation appeared in the case of n-type silicon wafers annealed for 5 s. On the other hand, the junction degradation together with the generation of three hole-trap levels H1(0.45 eV), H2(0.29 eV), and H3(0.3 eV) have been observed in boron-doped silicon using a short duration (5 s) plateau temperature between 850 and 1050 °C. Peak concentrations ranging from 1013 to 1014 cm−3 were measured after annealing at 1000 °C for the three hole traps. By increasing the plateau duration up to 20 s hole traps were no longer detected in boron-doped Czochralski-grown silicon. Moreover H2(0.29 eV) is stable at room temperature whereas both H1(0.45 eV) and H3(0.3 eV) decayed in unbiased samples after several weeks. A comparison of the trap properties with those of already known defect states suggested that residual 3D metal traces (Fe, V, Cr) might be responsible for all the observed defect states. In addition the intrinsic defects generated during the temperature plateau are likely to play a significant role in the final defect-state concentration after rapid thermal annealing.

On-chip picosecond time-domain measurements for VLSI and interconnect testing using photoconductors

Picosecond time-domain measurements of silicon IC interconnects were successfully performed using photoconductors integrated on-chip. Standard IC fabrication techniques followed by shadow-masked ion-beam irradiation were used to create the photoconductor/interconnect structures. Starting materials used were 70-Ω.cm n-type wafers and 16-Ω. cm p-type wafers. A subpicosecond pulsed laser system excited the photoconductors to produce and sample picosecond pulses on the Si substrate. These integrated photoconductors can also be used to perform picosecond transient measurements of VLSI devices and circuits. Optoelectronic cross-correlation measurements with photoconductor pulsers and photoconductor sampling gates were performed to characterize both the on-chip photoconductors and the on-chip interconnects. Photoconductors processed as pulsers produced electrical pulses with ∼ 2-ps rise time, ∼ 200-mV peak amplitude and full width at half-maximum (FWHM) of < 10 ps. Photoconductors processed as sampling gates demonstrated 3-dB measurement bandwidths of 20 GHz. Due to the absence of jitter on-chip signal delays were measured with subpicosecond precision.