Improvement of CMOS latch-up immunity using a high energy implanted buried layer

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In this CMOS latch-up study, we compared the dc latch-up properties of devices fabricated in a p-type non-epi wafer with a high energy implanted buried p + layer to those fabricated in a p-type epi layer over heavily boron doped p + substrate. A p-type non-epi wafer with an implanted buried p + layer was found to be more effective than a p/p + epi wafer in reducing substrate resistance. The implanted non-epi wafer showed a factor of 8 improvement over the epi wafer in the NPN induced latch-up immunity. No significant device degradation was observed for devices fabracated on high energy implanted wafers.