P-type SnO Thin-film Transistors Research Articles

Effect of Metal Capping Layer in Achieving Record High p-Type SnO Thin Film Transistor Mobility

Effect of Metal Capping Layer in Achieving Record High p-Type SnO Thin Film Transistor Mobility

Controlled orientation and microstructure of p-type SnO thin film transistors with high-k dielectric for improved performance

Despite its relatively high hole mobility, the electrical performance of p-type SnO thin-film transistors (TFTs) lags behind that of n-type oxide TFTs. In this study, we present an approach to enhance the performance of p-type SnO TFTs by utilizing an atomic-layer-deposited SnO/high-k structure, with crystalline HfO2 (c-HfO2) serving as a high-k dielectric. However, the grain boundaries on the c-HfO2 surface influenced the microstructure and orientation of the SnO layer, resulting in a random orientation and surface roughening. To address this issue, we modified the c-HfO2 surface with an amorphous ultrathin Al2O3 layer to eliminate the grain boundaries on the deposition surface. This enabled the alignment of the (00l) SnO planes parallel to the substrate surface and provided a smooth surface. Moreover, the introduction of ultrathin Al2O3 into SnO/high-k stacks substantially improved the electrical performance of p-type SnO TFTs. Our findings highlight the potential of integrating van der Waals semiconductors with high-k dielectrics, facilitating opportunities for advanced device applications.

High Field-Effect Mobility and On/Off Current Ratio of p-Type ALD SnO Thin-Film Transistor

High-performance p-type thin-film transistors (TFTs) with high field-effect mobility and high on/off current ratios (Ion/Ioff) were fabricated by engineering the microstructure and surface morphology of the atomic layer-deposited (ALD) SnO channel layer. ALD SnO films grown at a deposition temperature of 225 °C showed excellent crystallinity and dense, smooth surfaces, which resulted in superior field-effect mobility of 6.13–7.24 cm2/V·s without using a high-temperature postannealing process. Optimization of the SnO channel thickness suppressed the off-state leakage current, which consequently yielded excellent TFT switching performance, with an Ion/Ioff value of 104–105. Additionally, backchannel passivation by the ALD Al2O3 film improved the subthreshold swing characteristics by reducing surface defect states. These results suggest that synergistic control of the microstructure, surface morphology, and thickness of ALD SnO channels is crucial for achieving high-performance p-type SnO TFTs.

(Invited, Digital Presentation) Oxide TFTs Based on Semiconductors and Semimetals

Oxide semiconductors have opened a new era for large-area, flexible and transparent applications. Despite the progresses, a bottleneck issue of oxide thin-film transistors (TFTs) is the instability either under bias stress or when used as a current source. Furthermore, the carrier mobility and current driving capability need to be improved for high-spec displays. It is still hugely challenging to overcome both issues using the conventional device structure and oxide semiconductor materials.Here, we review our recent work on novel oxide TFTs that show a few desirable properties. Rather than using an ohmic metal contact as the source electrode, a high work-function Schottky source contact enables depletion around the TFT source region, which results in intrinsic immunity to the negative bias illumination stress, no obvious short channel effect, and superb current saturation over a wide range of drain voltage1. The flat saturation current gives rise to an extremely high voltage gain reaching 23,000, which is, to the best of our knowledge, the highest gain ever achieved by a solid-state transistor to date. The threshold voltage is also found to remain stable under different drain voltages, in contrast to standard TFTs, which may be useful in larger-area displays where the drain voltages of the drive TFTs can differ2. Furthermore, the depletion provided by the Schottky source electrode allows utilizing semi-metal ITO to replace IGZO as the TFT channel layer, which significantly enhances the carrier mobility and current driving capability. Other related work may also be discussed in the talk including oxide Schottky diodes operating beyond 10 GHz3, oxide TFTs operating beyond 1 GHz4, significantly enhanced carrier mobility by self-assembled monolayer treatment5,6, and CMOS-like oxide-based logic circuits7,8. References Extremely high-gain source-gated transistors, J Zhang, J Wilson, G Auton, Y Wang, M Xu, Q Xin, A Song, Proceedings of the National Academy of Sciences 116 (11), 4843-4848 (2019)Comparative Study of Short-Channel Effects Between Source-Gated Transistors and Standard Thin-Film Transistors, Zhenze Wang, Li Luo, Yiming Wang, Jiawei Zhang, and Aimin Song, IEEE Transactions on Electron Devices, 69(2), 561 - 566 (2022).Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz, J Zhang, Y Li, B Zhang, H Wang, Q Xin, A Song, Nature communications 6 (1), 1-7 (2015).Amorphous-InGaZnO thin-film transistors operating beyond 1 GHz achieved by optimizing the channel and gate dimensions, Y Wang, J Yang, H Wang, J Zhang, H Li, G Zhu, Y Shi, Y Li, Q Wang, Qian Xin, Zhongchao Fan, Fuhua Yang, Aimin Song, IEEE Transactions on Electron Devices 65 (4), 1377-1382 (2018).Significant Performance Improvement of Oxide Thin‐Film Transistors by a Self‐Assembled Monolayer Treatment, W Cai, J Zhang, J Wilson, J Brownless, S Park, L Majewski, A Song, Advanced Electronic Materials 6 (5), 1901421 (2020).Significant performance enhancement of very thin InGaZnO thin-film transistors by a self-assembled monolayer treatment, W Cai, J Wilson, J Zhang, J Brownless, X Zhang, LA Majewski, A Song, ACS Applied Electronic Materials 2 (1), 301-308 (2020).Complementary integrated circuits based on p-type SnO and n-type IGZO thin-film transistors, Y Li, J Yang, Y Wang, P Ma, Y Yuan, J Zhang, Z Lin, L Zhou, Q Xin, Aimin Song, IEEE Electron Device Letters 39 (2), 208-211 (2017).Thin Film Sequential Circuits: Flip-Flops and a Counter Based on p-SnO and n-InGaZnO, Y Yuan, J Yang, Y Wang, Z Hu, L Zhou, Q Xin, A Song, IEEE Electron Device Letters 42 (1), 62-65 (2020).

Mobility Enhancement in P-Type SnO Thin-Film Transistors via Ni Incorporation by Co-Sputtering

Oxide semiconductors have been considered one of the most promising candidates for flexible electronics applications owing to their low process temperatures and good reliability. However, the low mobility of p-type oxide semiconductors limits the performance of flexible oxide-TFT-based CMOS technology. In this study, p-type SnO_<i>x</i>:Ni thin films were deposited by reactive rf magnetron co-sputtering, a technique compatible with the current industrial semiconductor manufacturing technology, from Sn and Ni targets. As the Ni-gun power increased, the distribution of Ni in the SnO_<i>x</i>:Ni thin film changed from a more uniform dispersion to nanoclusters, resulting in the crystalline phase transition of SnO_<i>x</i>:Ni from <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>-SnO (110)-dominant polycrystalline to amorphous and then to <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>-SnO (101)-dominant polycrystalline. A high-mobility inverted-staggered p-type SnO_<i>x</i>:Ni TFT was then fabricated on a glass substrate with a maximum process temperature of 225&#x00B0;C, which is compatible with flexible polymeric substrates. The TFT fabricated at an optimal Ni-gun power of 42 W exhibited an impressive field-effect mobility of 11 cm²V^&#x2212;1s^&#x2212;1 and on current of <inline-formula> <tex-math notation="LaTeX">$35.2 ~\mu \text{A}$ </tex-math></inline-formula> per channel width-to-length ratio; these values are comparable to those of a typical n-type oxide TFT. These results should contribute toward flexible oxide-TFT-based CMOS technology.

Microwave and furnace annealing in oxygen ambient for performance enhancement of p-type SnO thin-film transistors

In this study, we investigated the effect of microwave-irradiation annealing (MWA) and thermal furnace annealing (FA) in oxygen ambient on the active channel layer of p-type tin-oxide (SnO) thin-film transistors. At very low source-drain voltage of −0.1 V, the MWA at 1200 W and FA at 300 °C samples have exhibited significant improvement in the electrical characteristics such as subthreshold swing (SS) of 0.93 and 0.485 V dec−1, the I on/I off ratio of 1.65 × 104 and 3.07 × 104, the field-effect mobility (μ FE) of 0.16 and 0.26 cm2 V−1 s and ultra-low off-state current of 1.9 and 2.0 pA respectively. The observed performance enhancement was mainly attributed to the reduction of interface trap density (N t) by tuning the power of MWA and optimizing the temperature in FA. From the result, we observed the optical band gap (E g) increased by 6% in FA, and 12% in MWA, which confirms improved crystallinity and reduction of defect states. Additionally, a low thermal budget microwave anneal process has shown high transmittance of more than 86% in the visible region (380–700 nm). The physical characterization indicates the partial phase transformation of SnO to SnO2 with retaining p-type conductivity in both annealing processes. The results demonstrate that both the annealing process could be highly promising to be used in the complementary logic circuits of new generation flexible/transparent displays.

Flexible Complementary Oxide Thin-Film Transistor-Based Inverter With High Gain

Wearable bio-sensing devices are considered promising for ubiquitous heath monitoring. To accurately read out small bio-signals, the development of high-performance flexible front-end circuits is crucial. Oxide semiconductors are considered one of the most promising active channel materials for on-polymeric-foil electronics. In this article, a high-gain flexible complementary metal–oxide–semiconductor (CMOS) inverter with a beta ratio of 1, a desirable feature for device miniaturization, was demonstrated by monolithically integrating a top-gated n-type indium gallium zinc oxide (IGZO) thin-film transistor (TFT) and a bottom-gated p-type SnO TFT on a 5.5- $\mu \text{m}$ -thick polyimide substrate. The influence of atomic layer deposited (ALD)-HfO2 capping layer on the properties of oxide active channels has been analyzed. The flexible inverter exhibited a high static voltage gain of 370 V/V and balanced noise margins (noise margin high of 4.8 V, noise margin low of 4.7 V) for a supply voltage of 10 V. In addition, the voltage transfer characteristics remained virtually unchanged when the device was subjected to an outward or an inward bending radius of 2.5 mm, indicating the complementary oxide-TFT-based inverter is practical for flexible electronics applications.

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer.

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

Experimental Investigation of Thermal Annealing and Ferroelectric Capacitor Area Effects for Hafnium-Zirconium Oxide Devices

In this study, we reveal that the thermal budget of post-metal annealing not only determines the formation of the ferroelectric phase and dipole domain but also the film quality of the gate stack in a metal-ferroelectric-metal capacitor. The higher leakage current caused by defect traps or grain boundaries within a gate stack would influence the stability of the ferroelectric domain switching. Furthermore, the ferroelectric domain switching and polarization current also depend on the ferroelectric capacitor area. We observe that a HfAlO ferroelectric capacitor can dominate the transfer characteristics of a p-type SnO thin-film transistor through the modulation of series capacitance in the gate stack based on a one-transistor one-capacitor series configuration. According to experimental results, the memory hysteresis window can be improved significantly with the area scaling due to the improvement of capacitance matching accuracy.

Effect of Mechanical Strain on Electrical Performance of Flexible P-Type SnO Thin-Film Transistors

This article investigates the effect of mechanical bending strain on the electrical performance and gate-bias stability of flexible p-type tin monoxide (SnO) thin-film transistors (TFTs). The on-polyimide SnO TFTs have an inverted-staggered structure with a back channel passivated by SiN x and HfO2 layers. The as-fabricated linear field-effect mobility, threshold voltage, subthreshold swing, and ON/OFF current ratio are 0.41 cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ , 0.74 V, 1.9 V/dec, and $1.1\times 10^{{4}}$ , respectively. The field-effect mobility decreases as the applied tensile strain increases, while it stays almost unaltered when a compressive strain is applied. A prominent increase of the positive-gate-bias-stress-induced threshold voltage shift is observed when the TFT is outwardly bent. The result shows that the mechanical tensile strain has a more significant impact on the electrical performance of p-type SnO TFTs.

Low-Voltage Metal-Oxide Thin Film Transistors Using P-Type Tin-Oxide Semiconductors.

In this paper, the effect of channel annealing and oxygen flow rate in P-type tin-monoxide (SnO) thin film transistor (TFT) was investigated to reach the process compatibility with n-type oxide-based TFT. The optimized P-type SnO TFT with a small threshold voltage of -0.1 V, a high field-effect mobility of 4 cm² V-1 s-1 and an on/off current ratio of >10² was proposed. From the experimental results, the 150 °C channel annealing revealed a metallic behavior but a semiconductor-like property at a higher 200 °C that was favorable for transistor rectification. Besides, the higher oxygen flow rate was also helpful for improving device mobility and driving current, but shows a slight increase in off-state leakage, which is unavoidable due to the increase of grain in SnO channel.

Radiation-Tolerant p-Type SnO Thin-Film Transistors

This present work investigated the effects of proton-beam irradiation on SnO-based p-type oxide thin-film transistors (TFTs) for the first time. The experiments were performed using a 5-MeV proton beam with doses ranging from $10^{12}$ to $10^{14}\,\,\textsf {p}\cdot \textsf {cm}^{-2}$ . The experimental results showed that the transfer curves of the p-type SnO TFT rarely changed following the proton irradiation at every irradiation condition, indicating that the p-type SnO TFT could be potentially useful in implementing complementary-logic-based oxide TFT circuits operating in harsh environments. The insensitivity of current conduction paths to SnO lattice disorder was considered as a possible mechanism for the observed radiation tolerance of the p-type SnO TFTs.

Effect of Plasma Fluorination in p-Type SnO TFTs: Experiments, Modeling, and Simulation

With experimental and numerical simulation, we report the origin of the performance enhancement in p-type SnO thin-film transistors (TFTs) due to fluorine plasma treatment (FPT). To study the effect of fluorination, using the reactive-ion-etching process, the devices are treated at various plasma powers upto 60 W. It is observed, through X-ray photoelectron spectroscopy and XRD measurements, that the plasma fluorination modifies the defect/trap states of SnO channel and SnO/HfO2 interface. These effects are introduced through density of state (DOS) model for SnO in numerical simulations, to understand the routes of electrical performance improvement. It is observed that the attributes of donor-like band-tail state and acceptor-like Gaussian defect states (Sn vacancies) are modified in overall DOS due to plasma fluorination. The treated device shows excellent electrical performances with high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~107 and low substhreshold swing of ~ 100 mV/dec and field-effect mobility ( $\mu _{\text {FE}}$ ) of 2.13 cm2V−1s−1.

Off-current reduction in p-type SnO thin film transistors

SnO is one of the few candidates for p-type oxide thin film transistors (TFTs) because it retains a reasonable high hole mobility in a nanocrystalline film. However, the high off-current of SnO TFT limits its usefulness. In this work, SnO TFTs were fabricated using thermal evaporation under ultra-high vacuum. In order to decrease the off-current in p-type SnO thin film transistors (TFTs), we used yttrium to reduce n-type minority charges in the channel. The on/off ratio of the TFT increases from 102 to 5 × 104 and the mobility of the TFT in the saturated regime reduces from 1.6 to 1.4 cm2/V s when the SnO channel is doped with 1 wt. % of Y. Grazing incidence X-ray diffraction and X-ray photoelectron spectroscopy reveal that the reduction of SnO2 in the Y-doped SnO TFT channel is the main reason for the improvement in the TFT characteristics.

Organic and inorganic passivation of p-type SnO thin-film transistors with different active layer thicknesses

Bottom gated thin-film transistors (TFTs) with various sputtered SnO active layer thicknesses ranging from 10 to 30 nm and different passivation layers have been investigated. The device with 20 nm SnO showed the highest on/off ratio of 1.7 × 104 and the smallest subthreshold swing of 8.43 V dec−1, and the mobility (0.76 cm2 V−1 s−1) was only slightly lower than in TFTs with a thicker SnO layer. However, both the mobility and the on/off ratio of the 15 nm SnO TFT dropped significantly by one order of magnitude. This indicated a strong influence of the top surface on the carrier transport, and we thus applied an organic or an inorganic encapsulation material to passivate the top surface. In the 20 nm TFT, the on/off ratio was doubled after passivation. The performance of the 15 nm TFT was improved even more dramatically with the on/off ratio increased by one order of magnitude and the mobility increased also significantly. Our experiment shows that polymethyl methacrylate passivation is more effective to reduce the shallow trap states, and Al2O3 is more effective in reducing the deep traps in the SnO channel.

Oxide Thin-Film Electronics using All-MXene Electrical Contacts.

2D MXenes have shown great promise in electrochemical and electromagnetic shielding applications. However, their potential use in electronic devices is significantly less explored. The unique combination of metallic conductivity and hydrophilic surface suggests that MXenes can also be promising in electronics and sensing applications. Here, it is shown that metallic Ti3 C2 MXene with work function of 4.60 eV can make good electrical contact with both zinc oxide (ZnO) and tin monoxide (SnO) semiconductors, with negligible band offsets. Consequently, both n-type ZnO and p-type SnO thin-film transistors (TFTs) have been fabricated entirely using large-area MXene (Ti3 C2 ) electrical contacts, including gate, source, and drain. The n- and p-type TFTs show balanced performance, including field-effect mobilities of 2.61 and 2.01 cm2 V-1 s-1 and switching ratios of 3.6 × 106 and 1.1 × 103 , respectively. Further, complementary metal oxide semiconductor (CMOS) inverters are demonstrated. The CMOS inverters show large voltage gain of 80 and excellent noise margin of 3.54 V, which is 70.8% of the ideal value. Moreover, the operation of CMOS inverters is shown to be very stable under a 100 Hz square waveform input. The current results suggest that MXene (Ti3 C2 ) can play an important role as contact material in nanoelectronics.

Complementary Integrated Circuits Based on p-Type SnO and n-Type IGZO Thin-Film Transistors

Oxide semiconductors are highly attractive for the new-generation transparent/flexible electronics. In this letter, logic gates (inverter, NAND, and transmission gates) and three-stage ring oscillators based on n-type indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) and p-type tin monoxide (SnO) TFTs are presented. The IGZO TFTs show a mobility of 10.05 cm $^{\textsf {2}}$ /( $\textsf {V}\cdot \textsf {s}$ ) and a threshold voltage of 5.00 V. The SnO TFTs exhibit a mobility of 1.19 cm $^{\textsf {2}}$ /( $\textsf {V}\cdot \textsf {s}$ ) and a matched threshold voltage of −5.05 V. At a supply voltage of 10 V, the complementary inverters show an extremely high gain of 112 with a geometric aspect ratio of 5. The dynamic responses of the logic gates based on n-type IGZO and p-type SnO TFTs are also examined. The delay time of the inverter measured from dynamic response is 27.75 $\mu \text{s}$ at a supply voltage of 10 V. The inverter, NAND, and transmission gates all exhibit ideal rail-to-rail output voltage behavior. At a supply voltage of 20 V, the three-stage ring oscillators are able to operate at 32.87 kHz, and the stage delay is $5.07~\mu \text{s}$ .

Charge Transport Mechanism in p-Channel Tin Monoxide Thin-Film Transistors

In this letter, we report on the charge transport mechanism in the p-type tin monoxide (SnO) thin-film transistors (TFTs) over a wide range of operation regimes and temperatures. From the temperature-dependent field-effect conductance measurements, the variable range hopping and the trap-limited band transport are considered as dominant charge transport mechanisms in the SnO TFT at temperatures below ~ 200 K (−73 °C) and above ~273 K (0 °C), respectively, in the subthreshold and transition regions. In the above-threshold region, the intrinsic field-effect mobility ( $\mu _{\mathsf {FEi}})$ decreases with an increase in temperature with a prefactor $\gamma \sim $ -0.36 in the $\mu _{\mathsf {FEi}}\sim {T}^{\gamma }$ law at temperatures ( ${T}\text{s}$ ) between RT and 353 K (80 °C). The observed temperature and gate overdrive voltage dependence of $\mu _{\mathsf {FEi}}$ suggests that the acoustic phonon scattering is the dominant physical mechanism limiting $\mu _{\mathsf {FEi}}$ in the p-type SnO TFT at realistic operating conditions [in the above-threshold region and at temperatures ranging from RT to 353 K (80 °C)].

Analysis of carrier transport and band tail states in p-type tin monoxide thin-film transistors by temperature dependent characteristics

Tin monoxide (SnO) has drawn much attention in recent years due to its high hole mobility, transparency, and potential for mass production. However, due to its metastable nature, the deposited film often contains multi-phases such as metallic tin and tin dioxide, which may degrade its electrical properties. Here, we presented the temperature dependent characteristics of p-type SnO thin-film transistors. The hole transport mechanism is dominated by band conduction at high temperatures and variable-range hopping at low temperatures. The maximum activation energy was found to be 308 meV, which denotes a bandgap of around 0.6 eV. The density of states was found to be 1.12 × 1021 cm−3 eV−1 at VG = −80 V, and 6.75 × 1020 cm−3 eV−1 at VG = 0 V, respectively.

Temperature-dependent electrical instability of p-type SnO thin-film transistors

The temperature-dependent electrical instability of p-type SnO thin-film transistors (TFTs) was investigated for various stress and temperature conditions. The fabricated SnO TFT was suitably passivated using an SU-8 organic layer to prevent environmental effects on the stress-induced instability. Under the negative gate bias stress, the transfer curves showed a parallel shift in the negative direction for every temperature studied (room temperature, 50 °C, and 80 °C). This result indicates that the transfer curve shift is mainly due to hole-trapping in the interface defect states of SnO TFTs. A much larger threshold voltage shift (ΔVth) was observed at higher temperatures for short stress times, but ΔVth became saturated under these conditions. This indicates that hole detrapping from the interface defect states is also accelerated at a high temperature when the stress time increases. During the recovery phase, the transfer curves shifted back toward the positive direction for each temperature point. The transfer curves moved in the positive direction with a large ΔVth when the recovery time was 10 s, but the recovery rate slowed significantly when the recovery time extended beyond 10 s. Under the positive gate bias stress, the transfer curve shifted in the positive direction, mainly due to the electron trapping in the interface defect states. Similar temperature-dependence was observed in the time dependence of ΔVth under the positive and negative gate bias stresses. During the recovery phase, the transfer curves moved back in the negative direction. The recovery rate increased with increasing temperature because of the accelerated electron detrapping from the interface defect states.