P-type Channel Research Articles

Heterogeneous Integration of Complementary Field-Effect Transistors for High-Performance Micro LED Displays.

This study investigates a micro light-emitting diode (µLED) pixel circuit using the heterogeneous integration of complementary field-effect transistors (CFETs). The CFETs are fabricated using a semiconductor layer composed of tellurium (Te) and indium-gallium-zinc oxide (IGZO) layers. Te and IGZO layers in the heterostructure IGZO/Te film exhibit hexagonal and amorphous phases, respectively, indicating that each layer maintains independent material characteristics. The fabricated IGZO/Te CFETs exhibit ambipolar behavior with a turn-on voltage of 2.0V and field-effect mobility of 0.74 and 1.42 cm2 V-1 s-1 for p-type and n-type channels, respectively. Inverters comprising IGZO/Te CFET and IGZO TFT exhibit inverting behavior. A µLED pixel circuit is designed using IGZO/Te CFETs based on pulse width modulation (PWM). The proposed circuit uses an inverter structure with IGZO/Te and IGZO to control the emission time, suppressing the wavelength shift of µLEDs depending on the µLED current levels. The operation of the proposed pixel circuit is investigated through simulation and measurement of the fabricated circuit. The fabricated µLED pixel circuit successfully exhibits PWM operation, controlling the emission time and luminance. Consequently, IGZO/Te CFETs show promise as devices for high-quality µLED displays.

Development of the Ge-MDST instrument structure with an induced p-type channel

The conditions for the growth of n-type Ge conduction layers by the HW CVD method with the parameters required to create a Ge-TIR transistor with an induced p-type channel are determined. The conditions of deposition by electron beam deposition and subsequent annealing of layers of a high-k dielectric ZrO2:Y2O3 are optimized, allowing to achieve a leakage current of 5 × 10–6 A/cm2. For the developed instrument structure, some parameters of the Ge-TIR transistor were calculated, such as the channel length, the maximum voltage between the drain and the source, and the breakdown voltage.

Junction Piezotronic Transistor Arrays Based on Patterned ZnO Nanowires for High-Resolution Tactile and Photo Mapping.

Recently, a great deal of interest has been focused on developing sensors that can measure both pressure and light. However, traditional sensors are difficult to integrate into silicon (Si)-based integrated circuits. Therefore, it is particularly important to design a sensor that operates on a new principle. In this paper, junction piezotronic transistor (JPT) arrays based on zinc oxide (ZnO) nanowire are demonstrated. And the JPT arrays show high spatial resolution pressure and light mapping with 195 dpi. Because ZnO nanowires are arranged vertically above the p-type Si channel's center of the transistor, the width of the heterojunction depletion region is constricted by the positive piezoelectric potential generated by strained ZnO. In addition, photogenerated charge carriers can be created in the Si channel when JPT is stimulated by light, which increases its electrical conductivity. Consequently, the external pressure and light distribution information can be obtained from the variation in the output current of the device. The prepared JPT arrays can be compatible with Si transistors, which make them highly competitive and make it possible to incorporate both pressure and light sensors into large integrated circuits. This work will contribute to many applications, such as intelligent clothing, human-computer interaction, and electronic skin.

Simulations of Anisotropic Monolayer GaSCl for p-Type Sub-10 nm High-Performance and Low-Power FETs.

Two-dimensional materials have been extensively studied in field-effect transistors (FETs). However, the performance of p-type FETs has lagged behind that of n-type, which limits the development of complementary logical circuits. Here, we investigate the electronic properties and transport performance of anisotropic monolayer GaSCl for p-type FETs through first-principles calculations. The anisotropic electronic properties of monolayer GaSCl result in excellent device performance. The p-type GaSCl FETs with 10 nm channel length have an on-state current of 2351 μA/μm for high-performance (HP) devices along the y direction and an on-state current of 992 μA/μm with an on/off ratio exceeding 107 for low-power (LP) applications along the x direction. In addition, the delay-time (τ) and power dissipation product of GaSCl FETs can fully meet the International Technology Roadmap for Semiconductors standards for HP and LP applications. Our work illustrates that monolayer GaSCl is a competitive p-type channel for next-generation devices.

A Common Source 3D FeFET with Disturb Inhibition Program and Erase Method

A common source p-type single-crystal channel three-dimensional ferroelectric field-effect transistor (3D FeFET) in a 2 × 2 × 3 array is proposed. Two programming and erasing conditions are introduced. A large memory window (>1.2 V), good retention (>10 years), and high speed (<100 ns) was presented under high voltage (±6 V) conditions. The endurance, >103, was observed under relatively low voltage (±3 V) conditions. Based on these two conditions, a novel asymmetric bias program and erase method is proposed to obtain good disturb inhibition. A more than 0.5 V threshold voltage shift in target cell was achieved while threshold voltage shift in unselected cell was limited, and analysis of long term disturb in novel method is proposed, showing good disturb inhibition. Additional investigation in word line disturbance shows causation and efficiency of disturb. Building upon the proposed structure of the 3D FeFET array, a vector matrix multiplication able to calculate 2-bit weights was designed and demonstrated. This work provides a potential solution for increasing integration density with 3D FeFET array.

Vertically Integrated Monolithic Neuromorphic Nanowire Device for Physiological Information Processing.

This study demonstrates the conceptual design and fabrication of a vertically integrated monolithic (VIM) neuromorphic device. The device comprises an n-type SnO2 nanowire bottom channel connected by a shared gate to a p-type P3HT nanowire top channel. This architecture establishes two distinct neural pathways with different response behaviors. The device generates excitatory and inhibitory postsynaptic currents, mimicking the corelease mechanism of bilingual synapses. To enhance the signal processing efficiency, we employed a bipolar spike encoding strategy to convert fluctuating sensory signals to spike trains containing positive and negative pulses. Utilizing the neuromorphic platform for synaptic processing, physiological signals featuring bidirectional fluctuations, including electrocardiogram and breathing signals, can be classified with an accuracy of over 90%. The VIM device holds considerable promise as a solution for developing highly integrated neuromorphic hardware for healthcare and edge intelligence applications.

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation.

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

Impact of P-type doping and channel length on the performance of 2D SiC MOSFET

The performance of monolayer two-dimensional SiC MOSFET with various concentration of p-type doping in source/drain region and various lengths of channel were investigated based on the density-functional theory method. All MOSFETs could realize dynamic turn-off. The maximum ON-state current were up to 1152.8 μA/μm and 1731.4 μA/μm for 4.1 nm and 5.1 nm SiC MOSFET with 5 × 1020 cm−2 doping concentration, respectively, which could satisfy the requirement of the high-performance devices outlined by ITRS for production year 2028. In addition, the various parameters (transmission spectra, the intrinsic gate capacitance and so on) of MOSFETs were studied. Moreover，the LDOS and spectral current under ON-state voltage were researched to further explore the physical mechanism of the MOSFETs. Furthermore, the study found that the current increased as the temperature increasing, the current value and the temperature difference between left and right electrode at the fixed bias voltage and gate voltage were not related.

Molecule-induced n-type behavior of phosphorene-based field-effect transistor for highly sensitive detection of sialic acid

Low-concentration detection of sialic acid (SA) seems to be a promising method in early cancer prognosis. In this work, a phosphorene-based field-effect-transistor (Ph-FET) device has been introduced for detecting various concentrations of SA. The device was fabricated using successive hydrogen plasma treatment to start from the red phosphorus layer and to realize highly crystalline black phosphorus sheets. The morphology and crystalline quality of phosphorene sheets have been extensively examined by transmission electron microscopy, scanning electron microscopy, atomic force microscopy, and Raman spectroscopy. By utilizing this device, we can detect different concentrations of SA from 3 to 2400 μM owing to its negative charge. The detection limit of SA is as low as 2.8 μM. This technique offers a straightforward method for the fabrication of high-performance Ph-FET with no need for exfoliation or sheet transfer. We have fabricated a Ph-FET with a mobility of 10 cm2 V−1 s−1, a carrier concentration of 3.9 × 1011 cm−2, and an on/off current ratio of 103. Moreover, we have observed that exposure to SA solution would change the carrier type of the transistor from a p-type channel into an n-type channel device due to the interaction of SA molecules with the phosphorene atoms at the top of the puckered structure that weakens the P-P lattice anti-bonding orbitals and screens the trapped sites.

Two-Dimensional Silver-Chalcogenolate-Based Cluster-Assembled Material: A p-type Semiconductor.

We have synthesized and characterized a new two-dimensional honeycomb architecture resembling a single-layer of atomically precise silver cluster-assembled material (CAM), [Ag12(StBu)6(CF3COO)6(4,4'-azopyridine)3] (Ag12-azo-bpy). The interlayer noncovalent van der Waals interactions within the single-crystals were successfully disrupted, leading to the creation of this unique structure. The optimized Ag12-azo-bpy CAM demonstrates a valence band that is localized on the Ag12 cluster node situated near the Fermi energy level. This localization induces electron injection from the linker to the cluster node, facilitating efficient charge transportation along the plane. Exploiting this single-layer structure as a distinctive platform for p-type channel material, it was employed in a field-effect transistor configuration. Remarkably, the transistor exhibits a high hole mobility of 1.215 cm2 V-1 s-1 and an impressive ON/OFF current ratio of ∼4500 at room-temperature.

The improvement of Schottky barrier diodes fabricated only by B ion implantation doping accomplished by refinement of the electrode structure

In this study, we fabricated p-type diamond Schottky barrier diodes (SBD) and performed selective B doping for the p-type channel and Ohmic region by double ion implantation. SBD were redesigned in the configuration and shape of Ohmic and Schottky electrodes to improve device characteristics. The fabricated device exhibited a rectification ratio of approximately 2400 because of decreasing the parasitic resistance to 2.7 × 107 Ω and the ideality factor to 2.7. The Schottky barrier height was obtained to be 1.04 eV. It is indicated that the diamond SBD fabricated only by B ion implantation is improved by refinement of the electrode structure.

Ballistic spin transport in DC-bias single top gate p-type narrow channel device with Zeeman–Rashba effects

The ballistic transport of holes in a p-type quasi-one-dimensional channel system is investigated without considering the coupling effect of the light and heavy holes. A top gate (TG) is used to form a potential barrier in the quantum channel with Zeeman–Rashba (ZR) effects. The Luttinger Hamiltonian and propagation matrix method are used to examine the relationship between the conductance and the incident hole energy. The results show that when the gate width L is large, an electron-like bound state (E-BS) structure is formed at the inflection point of the spin-down branch. When a positive gate potential energy is applied (U0>0), the light and heavy hole spins form an electron-like quasi-bound state (E-QBS) at the top of the branch under the hole spin. Conversely, when a negative gate potential energy (U0<0) is applied, the light and heavy hole spins form a hole-like quasi-bound state (H-QBS) structure at the bottom of the branch.

Simulation of a Steep-Slope p- and n-Type HfS2/MoTe2 Field-Effect Transistor with the Hybrid Transport Mechanism

The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs). In addition to the selection of source materials with linearly decreasing density-of-states-energy relations (D(E)s), in this study, we further verified, by means of a computer simulation, that a 2D semiconductor-semiconductor combination could also be used as an efficient CS. As a test case, a HfS2/MoTe2 FET was studied. It was found that MoTe2 can be spontaneously p-type-doped by interfacing with n-doped HfS2, resulting in a truncated decaying hot-carrier density with an increasing p-type channel barrier. Compared to the conventional MoTe2 FET, the subthreshold swing (SS) of the HfS2/MoTe2 FET can be significantly reduced to below 60 mV/decade, and the on-state current can be greatly enhanced by more than two orders of magnitude. It was found that there exists a hybrid transport mechanism involving the cold injection and the tunneling effect in such a p- and n-type HfS2/MoTe2 FET, which provides a new design insight into future low-power and high-performance 2D electronics from a physical point of view.

Undoped p-type ZnTe thin film and thin film transistor channel performance

Undoped p-type ZnTe thin film and thin film transistor channel performance

Suppression of p-type parasitic channel formation at the interface between the aluminum nitride nucleation layer and the high-resistivity silicon substrate

In this study, GaN-based epitaxial structures were grown on high-resistivity silicon (HRSi) substrates by metalorganic chemical vapor deposition. The p-type parasitic channels generated at the interfaces of the aluminum nitride (AlN) nucleation layers and HRSi substrates were characterized by surface capacity measurement, backside secondary ion mass spectrometry, and spread resistance profiling. The 2-nm thick silicon nitride (SiNx) layer formed by nitridation on the HRSi substrates was used to suppress the Al diffusion from the 50-nm AlN nucleation layer and also prevented from generation of the p-type parasitic channels. The p-type parasitic channels induced insertion losses at high frequencies. Transmission line measurement was used to determine the insertion losses. The insertion loss of the GaN-based epitaxial structure with the optimized 25-nm AlN nucleation layer on the 2-nm SiNx layer was -2.72 dB/mm. It was only 0.04 dB/mm higher than that of the annealed HRSi substrate (-2.68 dB/mm) at 10 GHz. Obviously, the diffusion of Al from the optimized 25-nm thick AlN nucleation layer into the HRSi substrate can be alleviated by the SiNx layer, thereby reduced insertion loss.

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit.[1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

Electrical and Optical Properties of P-Type NiO Films Grown Via Nickelocene Precursor in a Hollow-Cathode Plasma-ALD Reactor

Electrical and Optical Properties of P-type NiO Films Grown via Nickelocene Precursor in a Hollow-Cathode Plasma-ALD Reactor In contrast to the relative abundance of as-grown unintentionally doped n-type semiconductor materials, there are only a few alternative alloys showing p-type conduction without needing extra high-temperature doping processes. Among them, CuO, Bi2O3, SnO, and NiO represent the most widely studied metal oxides which exhibit native p-type properties. NiO is of particular interest mainly due to its stability and promising performance as hole-transport layers in emerging solar cell device structures. However, to broaden the NiO application domain towards potential back-end-of-the-line (BEOL) transistor devices as potential p-type channel layers, the transport properties of NiO needs to be improved significantly. While low-temperature thermal, plasma, and ozone-assisted ALD efforts have resulted in p-type NiO films with atomic-level precision and large-area uniformity, the hole mobility is far from being sufficient, typically lower than 1 cm2/Vs.In an attempt to enhance the hole transport properties in low-temperature as-grown NiO layers, in this study we have carried out a systematic study on plasma-enhanced ALD (PEALD) of NiO films on Si and glass substrates using nickelocene (NiCp2) and O2/Ar plasma mixture in two separate reactors: (i) 8” plasma-ALD reactor with a quartz-based inductively-coupled plasma (ICP) source; (ii) 4” plasma-ALD reactor with a stainless steel-based hollow-cathode plasma (HCP) source, equipped with an in-situ ellipsometer. 300 cycle ICP-ALD growth experiments with 300 W O2/Ar plasma at 150 °C substrate temperature were carried out to identify the optimal NiCp2 precursor temperature (50 - 110 °C) and observe the influence of precursor pulse time (0.1 - 1 s). Detailed saturation studies using in-situ ellipsometer monitoring were carried out in the HCP-ALD reactor, scanning for NiCp2 pulse time, O2 plasma exposure time, purge time, and plasma power. Optimal growth conditions were identified as 90 ms NiCp2 pulse / 5 s purge / 10 s O2-plasma at 100 W plasma exposure / 5 s purge. To check the growth linearity and obtain thicker films for materials characterization, 800 cycle runs were conducted to evaluate the substrate temperature impact (100 - 250 °C) on growth-per-cycle (GPC) and film properties. The last growth parameter studied was the plasma gas composition, where several O2/Ar mixtures (20/0, 20/20, 50/0 sccm) were tested at the optimal substrate temperature of 200 °C.The resulting NiO films are characterized for their structural, optical, and electrical properties. Films grown at optimal conditions (200 °C) exhibit refractive index values reaching 2.3, which is in good agreement with reported values for the best polycrystalline NiO films in the literature. NiO films deposited on both Si and glass substrates exhibit polycrystalline single-phase cubic structure (c-NiO). Hall measurements of the as-grown NiO layers on glass substrates, revealed film resistivity values about 40 and 150 ohm-cm for HCP and ICP samples, respectively. Post-deposition annealing within 200 – 400 °C temperature range resulted in a significant reduction of resistivity for more than two orders of magnitude. However, the relatively volatile and unstable Hall voltage values led to unreliable carrier concentration and Hall mobility values, therefore we were not able to confirm the type of transport via Hall measurements.In order to determine the carrier type and extract field-effect mobility values, we have fabricated vertical NiO/n-Si p-n junction diodes as well as NiO/Al2O3/Si thin-film-transistor (TFT) device prototypes to characterize diode I-V behavior and confirm p-type layer structure for NiO, and extract the field-effect carrier mobility, respectively. Our I-V measurement results confirmed p-n junction diode characteristics with decent ON/OFF ratios for forward and reverse diode current values. TFT characterization results and findings will be presented as well.

Influence of post-deposition annealing on the novel alloyed SnSxO1-x semiconductor in p-type thin-film transistors

SnO is an oxide semiconductor that has the potential to be used in the development of thin-film transistors (TFTs) with a p-type channel. SnO on the other hand is a metastable phase, and the oxidation of the SnO films makes high-performance TFTs with good mobility and high on/off current ratios challenging. In this study, based on the SnO–SnO2 phase transformation mechanism, a novel alloyed semiconductor SnSxO1-x was reported to prevent the conversion of SnO to SnO2. Pulsed laser deposition was used to grow SnO and SnSxO1-x thin films on Si/SiO2 substrates, which were then exposed to rapid annealing procedures. From Raman spectroscopic analysis, SnSxO1-x exhibited better antioxidant performance than pure SnO at the same post-deposition annealing process. The developed SnSxO1-x TFTs exhibited better stability and an improved on/off ratio than SnO TFTs after high-temperature annealing. Additionally, we fabricated bilayer SnSxO1-x/SnO thin-film transistors with typical p-channel conduction and a 10−11 A off-state current.

Enabling highly-efficient OLED with solution-processed nanocrystalline copper phthalocyanine hole-injection/transport layer

We report solution-processed nanocrystalline copper-phthalocyanine (CuPc) as a hole-injection/transport layer used to maintain efficient hole injection and transport into the emissive layer. The efficacies and efficiencies of the devices with nanocrystalline CuPc hole-transport layer and control device fabricated poly (3,4-ethylene dioxythiophene)-poly(styrene-sulfonate) (PEDOT:PSS) are investigated. As a result, organic light-emitting diode (OLED) employing the CuPc layer exhibits maximum efficiencies such as a power efficiency (PEmax) of 46.7 lmW−1 and an external quantum efficiency (EQE) of 12.1% along with a current efficiency (CEmax) of 44.1 cdA−1, which are expressively improved as comparing with PEDOT:PSS based control device. We also observed changes in PEmax from 32.1 to 39.7 lmW−1, CEmax from 40.3 to 51.7 cdA−1 and EQEmax from 13.0 to 16.2% in thermally activated delayed fluorescence emitter based OLEDs as PEDOT:PSS is replaced with CuPC. This enhancement in all OLED device performance may be attributed to the decreased hole injection barrier at the anode and emissive layer interface. Furthermore, CuPC has been incorporated as a p-type channel to fabricate thin-film transistors (TFTs). CuPC possesses good mobility as comparing with PEDOT:PSS. We believe that the CuPc layer is a promising candidate to achieve high-performance next-generation OLEDs for lighting applications and TFTs.