P-channel Tunnel Field-effect Transistor Research Articles

Design and simulation of P-TFET for improved ION/IOFF ratio and subthreshold slope using strained Si1−xGex channel heterojunction

The performance of TFET is limited by low ON state tunnel current. This paper introduces a novel p-channel tunnel field effect transistor (TFET) which incorporates a hetero-structure channel layer made of Si/intrinsic—SiGe. Also, tensile strained Si1−xGex p-type channel is used which enhances the device characteristics, where x is the Ge-mole fraction. The proposed structure exhibits a very small subthreshold swing and a high ON–OFF current ratio. The device characteristics are improved on the basis of theoretical principles and simulation results. The structure is improvised to achieve higher values for ON-current as compared to previously reported structures in literature. The average value of subthreshold swing and ION-current are found to be 59 mV/dec and 10−5 A/µm.

Design and analysis of energy efficient semi-junctionless n+n+p heterojunction p-channel tunnel field effect transistor

This paper investigates the electrical characteristics of a novel p-channel InAs-GaAs0.1Sb0.9 Semi-Junctionless Tunnel Field Effect Transistor (SJTFET). Unlike the conventional TFET with p-i-n (n-i-p) doping profile, the proposed structure has similar doping density in the source and channel regions, which not only facilitates simpler fabrication process, but also enables scaling of the device without a power penalty. In addition, in comparison with junctionless TFET with additional gate contact over the source region, the proposed device provides a steep slope transfer characteristics with gates just over the channel region, which simplifies fabrication of the device. The workfunction difference between the metal gate and the channel modifies the hole density in the channel. The sensitivity of SJTFET, expressed in percentage, is defined as the ratio of the standard deviation to the mean value of electrical parameters with respect to the variation of design parameters. The results reveal that the gate workfunction, source-channel doping density and channel thickness are critical design parameters that may dramatically affect the device performance. In addition, for optimizing the performance of SJTEFT, the 2D variation matrix of off-state current is calculated as a function of challenging design parameters. The main feature of the proposed device is that the off-state current and threshold voltage are less sensitive to the variation of gate length and drain voltage, which boosts scaling of the device in nanoscale regime.

Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio

A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current ( $I_{\mathrm{\scriptscriptstyle ON}}\sim 0.17~\mu \text{A}/\mu \text{m}$ at $\vert V_{G}\vert =0.5$ V after $V_{\mathrm {TH}}$ adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. $\sim 100$ mV/ decade up to 10 nA/ $\mu \text{m}$ ). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs.

Band-Offset Engineering for GeSn-SiGeSn Hetero Tunnel FETs and the Role of Strain

In this paper a simulation study of the effect of conduction and valence band offsets on the subthreshold swing (SS) of a double-gate tunnel field-effect transistor (TFET) with gate-overlapped source is presented. The simulations show that if the pn-junction and the hetero-junction coincide, the band offsets can significantly improve the SS by suppressing the so-called point tunneling at the pn-junction. It turns out that the performance of an n-channel TFET is determined by the direct conduction band offset whereas that of a p-channel TFET is mainly effected by the energy difference between the light hole bands of the two materials. Thus, the performance of the hetero-junction TFET can be improved by selecting material systems with high conduction or valence band offsets. The misalignment between the pn-junction and the hetero-junction is shown to degrade the SS. The above-described band-offset engineering has been applied to the GeSn/SiGeSn hetero-structure system with and without strain. Simulations of GeSn/SiGeSn hetero-TFETs with band-to-band-tunneling parameters determined from pseudopotential calculations show that compressive strain in GeSn widens the design space for TFET application while tensile strain reduces it.

Study of gate leakage current paths in p-channel tunnel field-effect transistor by current separation measurement and device simulation

Scaling the gate dielectric is a key to improving the steep switching characteristics of tunnel field-effect transistors (TFETs). The effect of the gate leakage current caused by this scaling has not fully been investigated until now. In this work, gate leakage current paths in a p-channel TFET are experimentally investigated by designing three types of measurement setup for separating the current paths. Our measurements reveal that the so-called gate-edge leakage current that directly flows from the gate into the source adversely affects the subthreshold characteristics of the source current. We also report that the areal leakage current tunneling from the gate to the channel causes the OFF current to increase. A device simulation is performed to separate the contribution of electron gate tunneling from that of hole gate tunneling and to understand the mechanism underlying these tunnelings, which reveals that electron tunneling occurring in the nanometer-scale source–gate overlap determines the gate leakage. Structural engineering around the source–channel overlap plays an important role in achieving high-performance TFETs.

Can p-channel tunnel field-effect transistors perform as good as n-channel?

We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.

The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High-$\kappa$ Gate Dielectric

Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant κ of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that the fringing field arising out of a high-κ gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing field is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling. On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high- κ gate dielectric is used in it, as expected. It is also found that a low- κ spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structure.

Double Dielectric Spacer for the Enhancement of Silicon p-Channel Tunnel Field Effect Transistor Performance

A double dielectric spacer concept is proposed for the enhancement of the performance of silicon p-channel tunnel field effect transistor. The double dielectric spacer consist of an inner layer made of a high-k material and an outer layer made of a low-k material. We show that the double dielectric spacer with high-k inner layer result in the concentration of the external fringe field near the source to channel junction, resulting in the improvement of ON state currents without degrading the OFF state current or the subthreshold swing. Further we have illustrated improved dynamic performance of the double dielectric spacer architecture using mixed mode simulations of unloaded and capacitively loaded inverter circuits for the first time. Performance improvements are illustrated and explained for silicon dioxide, aluminium oxide and hafnium oxide gate dielectrics.

Investigation of Novel Si/SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors

This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p–i–n p-channel tunnel field-effect transistors using extensive device simulations. Three different device architectures are compared. It is shown that depending on the Ge mole fraction in SiGe and the gate voltage, the tunneling could be from the channel to source or within the source only. Due to this, a very careful optimization of the Ge mole fraction is required to achieve optimum performance. It is also shown for the first time that a vertical gate induced source tunneling is present in the devices and that this could be utilized for improving ON state current by increasing the gate–source overlap. Of the three device architectures compared, the structure with SiGe channel and Si source/drain is found to give better ON state current. Gate length scalability is found to be superior for the structure with SiGe source, and Si channel/drain.

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Experimental results of p-channel silicon vertical tunnel field-effect transistors down to sub-50 nm channel length are shown. As predicted by two-dimensional simulations, we show that the device on-current is nearly independent of channel length scaling. As the drain current is determined by electrons tunneling from the valence band to the conduction band, we show that mobility does not play any role in determining the device characteristics. Low temperature measurements reveal weak positive temperature coefficient in the transfer characteristics due to the dependence of bandgap on temperature. However, as expected for the silicon devices, low on-current is observed. Thus, we propose a lateral tunnel FET on SiGe-on-insulator with high on-currents and symmetric performance in n-channel as well as p-channel operating modes.