P-channel SOI MOSFETs Research Articles

Subbandgap Optical Differential Body-Factor Technique and Characterization of Interface States in SOI MOSFETs

A distribution of interface states <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(D_{\rm it})$</tex></formula> in SOI MOSFETs has been characterized by a subbandgap optical differential body-factor (SODBoF) technique. We adopted a subbandgap <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(E_{\rm ph} &lt; E_{g})$</tex></formula> optical source as a virtual gate on the body-contactless SOI MOSFETs under the subthreshold <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm GS} &lt; V_{T})$</tex></formula> current–voltage characteristics. Employing a differentiation to the body factor, any possible error from the threshold voltage is also suppressed. We applied the SODBoF technique to n- and p-channel SOI MOSFETs on the same wafer and verified the result. Extracted traps over the bandgap ranges <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$D_{\rm it} = \hbox{10}^{10} {-} \hbox{10}^{11}\ \hbox{cm}^{-2}\cdot \hbox{eV}^{-1}$</tex></formula> with a typical U-shape.

Performance of SOI MOSFETs with Ultra-Thin Body and Buried-Oxide

The electrical characteristics in ultra-thin (8 nm) SOI-MOSFETs with 10 nm buried oxide thickness were studied. Threshold voltage was effectively controlled for both of N-channel and P-channel SOI-MOSFETs even in the short devices (45 nm). No degradation of the mobility due to the use of thin buried oxide could be detected. Through appropriate back-gate biasing, the performance of ultra-thin SOI-MOSFETs can be improved dramatically. In P-channel SOI-MOSFETs, the hole mobility measured in volume conduction regime is higher than when only one interface (Si/high-K or Si/SiO2) is activated. This gain makes the hole mobility comparable with the universal mobility law and is promising for performance enhancement in CMOS circuits.

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO 2 gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.

Front- and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method

The carrier mobility in ultrathin SOI MOSFETs with thin SiO 2 gate oxide is investigated by comparing the front and back channels. The front-gate split CV method is used at large substrate voltages to determine the carrier density and mobility in the back channel. The implementation of the split CV technique in ultrathin SOI films is described. This method is also efficient for determining the threshold voltage of the back channel. The accuracy as well as the limitations of the technique are discussed. Systematic experiments are presented for advanced n-channel and p-channel SOI MOSFETs. The results confirm that the mobility in the front channel is smaller than that in the back channel.

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

Some interesting observations of hot carrier stress induced aging effects across various SOI CMOS technologies are reported in this paper. First, the influence of the floating-body strength on the hot-carrier induced degradation in N-channel 90 nm partially depleted SOI MOSFETs is investigated. Enhanced hot-carrier degradation with increasing floating-body strength is observed and possible physical mechanisms to explain the obtained results are suggested. A channel width dependent degradation mechanism, arising from the SOI nature is observed: lower degradation obtained for the narrower channels is attributed to the weakening of floating-body effect with decreasing channel width. In addition, measured data provide experimental evidence of a shift in the location of the damage in the channel further away from the drain at elevated temperatures which may be responsible for the enhanced saturation current degradation obtained when stressing the devices at elevated temperatures. With regard to P-channel SOI MOSFETs, an investigation of the aging/recovery mechanisms is carried out under various stress bias conditions. It is found that worst case degradation occurs at stress under high gate/high drain bias rather than the conventional low gate/high drain bias, which at closer examination it is actually found to be mainly due to concurrent Negative Bias Temperature stress, accelerated by device self-heating.

Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs

In this paper a comprehensive study of the worst case hot carrier stress conditions for p-channel partially depleted SOI MOSFETs is carried out. It is found that while stress at maximum gate current results to the conventional PMOSFET degradation mechanism (i.e., electron trapping in the gate oxide on the drain side), significant damage is also introduced following stress at the high gate/high drain voltage ( V G = V D) condition. A series of experiments unambiguously demonstrate that this damage is not caused by hot hole injection and that device degradation mechanism at V G = V D stress condition (formation of interface states and positive oxide charges) is in fact due to negative bias temperature instability which is activated because of the self-heating effect. In addition, stress at high temperature is found to result in a shift of the worst case stress condition from maximum gate current to V G = V D.

Hot electron induced punchthrough voltage of p-channel SOI MOSFET’s at room and elevated temperatures

Hot electron induced punchthrough voltage of p-channel SOI MOSFET’s at room and elevated temperatures

A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V/sub d/=V/sub t/,V/sub d//2 or V/sub d/) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO/sub 2/ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress.

Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 /spl mu/m down to 0.1 /spl mu/m. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V/sub g//spl ap/V/sub d/), maximum substrate current (V/sub g//spl ap/V/sub d//2) and parasitic bipolar transistor (PBT) action (V/sub g//spl ap/0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range.

Hot-carrier effects in deep submicron SOI MOSFETs

Hot carrier effects are investigated thoroughly in deep submiron N- and P-channel SOI MOSFETs, for gate lengths down to sub-0.1 μm. In particular, the hot-carrier-induced degradations of these devices are analyzed in the light of photon emission and gate current experiments. It is shown that the hot carriers which lead to the degradation of the main electrical parameters of deep submicron SOI MOSFETs are created by various mechanisms (MOS and/or parasitic bipolar transistor carrier transport) depending on the channel length, the carrier type and the biasing conditions. In this respect, for N-channel SOI devices the worst case for the device lifetime can be either the maximum gate current condition ( V g = V d), or the maximum substrate current condition ( V g ≈ V d 2 ), or the PBT condition ( V g = 0). However, for P-channel devices the maximal transistor aging is always obtained in the case of maximal gate current ( V g = V d).

Design of Si and SiGe p-channel SOI MOSFET

There is a great deal of interest in combining SOI and SiGe technologies. In this work we present a systematic study of scaling properties of n + and p + gate SOI Si and SiGe p-MOSFETs by using two-dimensional numerical simulation. It was found that for both Si and SiGe devices, n + gate is better suited for the design of fully depleted devices while for the design of partially depleted or near-fully depleted devices p + gate is a better choice. Overall, the n + gate is a better solution since we can design a device that is very low doped, fully depleted, satisfies all the design criteria, has small threshold voltage ( V TH) sensitivity to the silicon film thickness ( t Si) and sharp subthreshold slope. The SiGe device shows increase in linear transconductance of 24%, smaller increase in saturation transconductance, improved current drive and extended range of design options. Our results also indicate that reduction of the t Si is more effective in controlling the DIBL and SCE in low doped n + gate designs, than increase in doping. The n + gate design requires p + doping spike for threshold voltage adjustment. For the case of Si p + gate design, V TH can be easily adjusted by changing the doping level in the channel. Since the doping level used is relatively high this naturally leads to partially depleted devices in order to avoid large dependence of V TH on the t Si. However, a fully depleted device can be designed to have low dependence of V TH on the t Si. This is done by utilizing the t Si dependence of: (1) the total charge under the gate; and (2) source-body potential barrier. If the thickness is reduced, the first effect reduces while the second one increases the threshold voltage making the dependence of V TH on the thickness acceptable. The p + gate SiGe SOI p-MOSFET requires high body doping levels and exhibits large subthreshold slope and reduced transconductance.

An analytical back gate bias dependent subthreshold swing model for accumulation-mode p-channel SOI MOSFETs

An analytical back gate bias dependent subthreshold swing model of the accumulation-mode p-channel SOI MOSFETs is derived using the exponential dependence of the carrier concentrations on the potential through the silicon film. The subthreshold swing is shown to be proportional to the reciprocal of the derivative of the minimum potential through the silicon film with respect to the front gate voltage. The subthreshold swing is compared to that in the enhancement-mode devices, and its dependencies on device parameters and back gate bias are studied. Based on the model, a method of extraction of front and back interface trap densities in these devices from subthreshhold swing is suggested.

Experimental investigation and numerical simulation of low-frequency noise in thin film SOI MOSFETs

The low-frequency noise in N- and P-channel SOI MOSFETs is studied experimentally and by numerical simulations. The behavior of fully depleted devices with thin silicon film is investigated for various substrate biases and film dopings. The importance of volume inversion, which induces a decrease of the noise, is stressed.

Transient effects in accumulation mode p-channel SOI MOSFET's operating at 77 K

This paper critically examines the conduction mechanisms in accumulation mode p-channel SOI MOSFET's operating at cryogenic temperatures. In particular, attention is given to the body current component, which in most cases is experimentally not observed at 77 K or 4.2 K. As will be demonstrated, both the body current and the back accumulation current show pronounced transient effects at low temperatures, which are related to the slow generation/recombination of minority carriers. This is caused by deep depletion from the front interface, which suppresses these current components. By the application of either a light pulse or a large drain voltage V/sub ds/ minority carriers are generated nearly instantaneously in the body region, rendering the body and the back accumulation components clearly visible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Subthreshold slope of long-channel, accumulation-mode p-channel SOI MOSFETs

An analytical model for the subthreshold slope of the accumulation-mode p-channel SOI MOSFET is developed. The exact solution of the equations reveals that the subthreshold swing is slightly larger (by a few percent) than that of enhancement (inversion-mode) fully depleted SOI devices. In most cases, however, the classical subthreshold slope expression developed for inversion-mode fully depleted SOI MOSFET can be used as a good approximation for accumulation-mode devices, which means that the subthreshold swing tends to the ideal value of S 0 = kT/ q ln(10) mV/dec if the buried oxide is sufficiently thick and if the interface trap density is sufficiently low.

Analysis of the latch and breakdown phenomena in N and P channel thin film SOI MOSFET's as a function of temperature

A study of the latch and breakdown phenomena in thin film N- and P-channel SOI MOSFET's is performed as a function of temperature. For P-type MOSFET's, for which no investigation of the parasitic bipolar transistor has been carried out, we show that latch problems are observed in the subhalf-micrometer range, while this feature is emphasized in the micrometer range for N-channel transistors. In addition, it is demonstrated by theoretical considerations and experimental results that these parasitic effects are strongly reduced at liquid nitrogen temperature and vanish almost entirely at liquid helium temperature. Similar improvements are obtained at low temperature in both N and P-channel SIMOX MOSFET's. >

Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures

The threshold voltage for the three different conduction components of an accumulation-mode PMOS SOI were experimentally extracted at room and liquid-helium temperatures. A deep-depletion transient effect was observed to play an important role when one of the interfaces was in inversion, even at room temperature. An intuitive physical interpretation is given for the suppression of some current components at liquid-helium temperatures. In addition, a simple model for calculating the silicon-film thickness and the doping level is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10/sup 4/, and the source-drain leakage current is decreased by a factor of 10-10/sup 2/ compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs. >

Problems in designing thin-film accumulation-mode p -channel SOI MOSFETs for CMOS digital circuit environment

A back-accumulation conduction mechanism ignored in previously-published analyses is shown to be the prime factor in the definition of the threshold voltage of the thin-film accumulation-mode p-channel SOI MOSFET when the device is integrated in a typical digital circuit environment. A new formulation which overcomes this problem is presented, then used to discuss problems of a tradeoff between film doping and threshold voltage as a function of other technological parameters.

Short channel effect in thin-film accumulation-mode p -channel SOI MOSFETs

A short channel effect in thin-film accumulation-mode p-channel SOI MOSFETs is investigated. It is observed that a significant leakage current can flow in a short-channel p+pp+-device when it is turned off. Two dimensional numerical simulations reveal that the nature of this current in short-channel SOI MOSFETs is due to the combination of potential barrier lowering effects caused by the presence of a negative back-gate bias and that of a large drain voltage.