P-channel Power VDMOSFETs Research Articles

Impact of negative bias temperature instability on p-channel power VDMOSFET used in practical applications

Impact of the negative bias temperature instabilities (NBTI) on p-channel power vertical double diffused MOS (VDMOS) transistors was a subject of extensive research in previous years. It was shown that NBT stressing leads to degradation of some parameters, and among them, threshold voltage shift (ΔVT) was marked as one of the most important ones, because it directly impacts the lifetime in practical applications. Our earlier papers were primarily dealing with NBTI effects and responsible mechanisms in p- and n-channel power VDMOS transistors. However, this paper investigates NBTI effects in p-channel power VDMOSFETs under both static and different types of pulsed stressing signals, and their impact on the performances and reliability of DC motors driven by investigated devices.

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Experiments have done with the goal to obtain data for modeling. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.

Effects of pulsed negative bias temperature stressing in p-channel power VDMOSFETs

Our recent research of the effects of pulsed bias NBT stressing in p-channel power VDMOSFETs is reviewed in this paper. The reduced degradation normally observed under the pulsed stress bias conditions is discussed in terms of the dynamic recovery effects, which are further assessed by varying the duty cycle ratio and frequency of the pulsed stress voltage. The results are analyzed in terms of the effects on device lifetime as well. A tendency of stress induced degradation to decrease with lowering the duty cycle and/or increasing the frequency of the pulsed stress voltage, which leads to the increase in device lifetime, is explained in terms of enhanced dynamic recovery effects.

NBTI related degradation and lifetime estimation in p-channel power VDMOSFETs under the static and pulsed NBT stress conditions

The effects of static and pulsed NBT stressing on threshold voltage in p-channel power VDMOSFETs are analysed, and the results are compared in terms of the effects on device lifetime. The results obtained by both “1/VG” and “1/T” models, which are used for extrapolation to normal operation voltages and temperatures, respectively, indicate the device lifetime could be much longer under the pulsed stress conditions than under the static ones. It is also shown that lifetime tends to increase with decreasing the duty cycle of pulsed stress voltage applied.

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced Δ V T can be reduced to a quarter of Δ V T found after the static NBT stress.