Abstract
Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Experiments have done with the goal to obtain data for modeling. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.
Highlights
As the device dimensions in CMOS technologies have been continuously scaled down, a phenomenon called Negative Bias Temperature Instability (NBTI) has gained in importance as one of the most important degradation mechanisms
Degradation of transistor parameter values due to NBTI has emerged as a major reliability concern in current and future technology generations, especially in p-channel MOSFETs [1,2,3]
Impacts of static negative bias temperature stressing in p-channel power VDMOSFETs IRF9520 have been reported
Summary
As the device dimensions in CMOS technologies have been continuously scaled down, a phenomenon called Negative Bias Temperature Instability (NBTI) has gained in importance as one of the most important degradation mechanisms. N. Mitrović et al.; Informacije Midem, Vol 50, No 2(2020), 205 – 214 effects are manifested as the changes in device threshold voltage (VT), transconductance (gm) and drain current (ID), and have been observed mostly in p-channel MOSFETs operated under negative gate oxide fields in the range 2 - 6 MV/cm at temperatures around 100 °C or higher [1,2,3,4,5]. Mitrović et al.; Informacije Midem, Vol 50, No 2(2020), 205 – 214 effects are manifested as the changes in device threshold voltage (VT), transconductance (gm) and drain current (ID), and have been observed mostly in p-channel MOSFETs operated under negative gate oxide fields in the range 2 - 6 MV/cm at temperatures around 100 °C or higher [1,2,3,4,5] Change in these parameters is dependent on the stress parameters (time, temperature, gate voltage). Considering the effects of NBTI related degradation on device electrical parameters, NBT stressinduced threshold voltage shift (∆VT) seems to be the most critical one [6, 7]
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