P-channel LDMOS Research Articles

An Improved SOI P-Channel LDMOS With High- ${k}$ Gate Dielectric and Dual Hole-Conductive Paths

An improved p-channel lateral double-diffused MOSFET (pLDMOS) with silicon-on-insulator substrate is proposed. On one hand, the improvement is attributed to a dielectric film with high permittivity (high-k), which is employed at the silicon surface to optimize the electric field distribution. Thus, the drift region dose could be increased, while its deviation has less influence on the breakdown voltage (BV). On the other hand, an additional pLDMOS is introduced to form another hole current path, which contributes to a decreased specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). The simulation results show that the proposed structure exhibits a BV of 366 V and an Ron,sp of 24 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , at a back gate bias of -200 V. Compared with the previous one, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is decreased by 39%, and the dose deviation window of the drift region for ensuring the breakdown voltage above 300 V is relaxed from ±2% to ±5%.

Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process

Large array devices (LAD) of MOSFETs are needed in most power ICs. NMOS transistors are used in current sinking while PMOS in current driving. Unlike the NMOS transistors, the high voltage PMOS transistors (HVPMOS) electrostatic discharge (ESD) self-protection of LAD for higher than 30V applications are less extensively studied. In this paper, the device level improvements of the 60V HVPMOS LAD of a 0.25μm BCD process is studied to obtain good ESD protection margins. The effects of device and layout optimization guidelines are also examined. Furthermore, the developed approach is shown to be a low cost general solution for the HVPMOS LAD with poor ESD self-protection capability in a 0.25μm BCD process.

A 300-V Ultra-Low-Specific On-Resistance High-Side p-LDMOS With Auto-Biased n-LDMOS for SPIC

In this paper, a high-side p-channel LDMOS (p-LDMOS) with an auto-biased n-channel LDMOS (n-LDMOS) based on Triple-RESURF technology is proposed. The p-LDMOS utilizes both carriers to conduct the on-state current; therefore, the specific on-resistance ( $R_{{\rm on},{\rm sp}}$ ) can be much reduced because of much higher electron mobility. The simulation result shows that the proposed 300-V p-LDMOS obtains a $R_{{\rm on},{\rm sp}}$ of 16.97 mΩ/cm2, which is about 65% reduced compared with the Triple-RESURF silicon limit and is comparable to an optimized n-LDMOS (BV = 340 V, $R_{{\rm on},{\rm sp}} = 18$ mΩ/cm2 ). In addition, due to larger current capability, the active area of the proposed p-LDMOS is only about one third of an optimized Triple-RESURF p-LDMOS. The turn-on ( $t_{r}$ ) and turn-off time ( $t_{f}$ ) are reduced by 51.2% and 40.0%, compared to the optimized Triple-RESURF p-LDMOS, respectively.

Robust reliability and electrical performances by the bulk-contact modulation in 60-V p-channel LDMOS power components

ABSTRACTTo increase reliability and electrical performance, shallow-trench isolation (STI) (or called field-oxide (FOX)) structures were inserted in the bulk-contact region of 60-V high-voltage p-channel lateral-diffused MOSFET (pLDMOS) devices in this study. As the FOX ratio increased with the addition of FOX segments, the value of the secondary breakdown current (It2) was enhanced. Therefore, the anti-electrostatic discharge ability of a pLDMOS device can be efficiently improved using this novel method. In addition, when the weighting ratio of FOX structures increased, variation values in the trigger voltage (Vt1) and holding voltage (Vh) of the corresponding samples remained within the range of approximately 1–4 V. The Ron value decreased because of more uniform conduction. The experimental data for the FOX structures added to the bulk revealed that the It2 value was improved by approximately 13.98%, Vh values were greater than 60 V (which is favorable for latch-up immunity), and the Ron value was decreased by approximately 12.62% compared with a reference device under test (without FOX segments in the bulk-contact region).

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

AbstractHow to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side isP+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2values have reached above 6 A; however, the major repercussion is that the Vhvalue will be decreased about 66.7 ~ 73.7%.

Design of Reliability Improvement in HV p-Channel LDMOS DUTs by a 0.25μm 60-V BCD Process

Design of Reliability Improvement in HV p-Channel LDMOS DUTs by a 0.25μm 60-V BCD Process

200-V High-side thick-layer SOI field p-channel LDMOS with multiple field plates

A high-voltage thick layer SOI field p-channel LDMOS (pLDMOS) with multiple field plates based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. Multiple field plates constructed by polysilicon and metal layer are adopted to modulate electric field distribution of the depleted drift region. The SOI field pLDMOS with off-state breakdown voltage (BV) of −240 V is experimentally realized, which can be widely used for simplifying the design of level shifting.

Back gate induced breakdown mechanisms for thin layer SOI field P-channel LDMOS

The back gate (BG) induced breakdown mechanisms for thin layer SOI Field P-channel LDMOS (FPLDMOS) are investigated in this paper. Surface breakdown, bulk breakdown and punch-through breakdown are discussed, revealing that the block capability depends on not drain voltage (Vd), but also BG voltage (VBG). For surface breakdown, the breakdown voltage (BVs) increases linearly with VBG increasing. An expression of BVs on VBG is given, providing a good fitting to measured and simulated results. Bulk breakdown with a low breakdown voltage is attributed to high VBG. VBG induces depletion in n-well, giving rise to punch-through breakdown. A design requirement for the thin layer SOI FPLDMOS is proposed that breakdown voltages for the three breakdown mechanisms are compelled to be higher than the supply voltage of switching IC.

The role of cold carriers and the multiple-carrier process of Si–H bond dissociation for hot-carrier degradation in n- and p-channel LDMOS devices

We apply our hot-carrier degradation (HCD) model, which uses the information about the carrier energy distribution, to represent HCD data measured in n- and p-channel LDMOS transistors. In the first version of our model we use the spherical harmonics expansion approach to solve the Boltzmann transport equation (BTE), while in the second version we employ the drift–diffusion scheme. In the latter case the carrier energy distribution function is approximated by an analytic expression with parameters found using the drift–diffusion scheme. The model, which has already been verified with nLDMOS transistors, is used to represent the carrier distribution functions, interface state density profiles, and changes of the drain currents vs. stress time in pLDMOS transistor. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. We check the validity of the model by neglecting the effect of cold carriers in HCD modeling in the case of nLDMOS devices stressed at high voltages. In our model, cold carriers are represented by the corresponding term in the analytic formula for the carrier distribution function as well as by the multiple-carrier process of the Si–H bond dissociation. We show that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

250 V Thin-Layer SOI Technology With Field pLDMOS for High-Voltage Switching IC

A 250 V thin-layer SOI technology based on a 1.5- $\mu \text{m}$ -thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 $\mu \text{m}$ to only 1.5 $\mu \text{m}$ . The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird’s beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of −329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS=−60V, VGS=0V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25nm gate oxide thickness, the threshold voltage of 5nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

A low specific on-resistance ( \(R_{{{\rm \mathrm{{\scriptstyle ON}},sp}}}\) ) silicon-on-insulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFF-state, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low \(R_{\rm {\scriptstyle {ON,SP}}}\) and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and \(R_{\rm {\scriptstyle {ON,SP}}}\) . Compared with the p-top SOI pLDMOS, the proposed device reduces the \(R_{\rm {\scriptstyle {ON,SP}}}\) by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.

Thin silicon layer p-channel SOI/PSOI LDMOS with interface n+-islands for high voltage application

A novel thin silicon layer p-channel SOI/PSOI LDMOS with interface n+-islands (INI PLDMOS) is studied in this paper. Interface n+-islands can not only accumulate interface charges to enhance the electric field of buried oxide layer (BOX) (EBOX) and achieve a high breakdown voltage (BV), but also form double-RESURF effect with p- drift region and improve the trade-off of the specific on-resistance (Ron,sp) and BV. The work mechanism of the proposed p-channel LDMOS is discussed. BV>1000V is obtained for the INI PLDMOS based on a 1.5-μm silicon layer and 2-μm BOX.

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (VBR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (Ron-sp/VBR trade-off) and dynamic (Ron × Qg) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor Ron-sp/VBR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance.

0.18um Scalable 7~45V pLDMOS for Smart Power Application

This work describes a 0.18um CMOS process based wide range scalable p-channel LDMOS transistor which targeted for power management application. The scalable pLDMOS is to use one process to cover different operation voltage devices, with the drain voltage scaling the device's specific on resistance (Rdson) must be always kept at a reasonable level and it is comparable with standalone technologies. The rated drain voltage can be continuously operated from 7V up to 45V, mean while the corresponding blocking voltage and Rdson are at 14V/6.5 mohm.mm2 and 60V/102 mohm.mm2 respectively.

Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Numerical TCAD and transmission line pulse analysis of an electrical safe operating area of a robust p-channel lateral DMOS transistor is performed. The observed independence of the trigger current on the applied gate-source voltage is attributed to a lack of quasi-saturation effect which is usually observed in an n-channel LDMOS. The dependence of the trigger voltage on the length of channel and drift regions is also analyzed, and the tradeoff with the specific on-resistance (RDSon) is given.

Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.