P-channel Field Effect Transistors Research Articles

Publisher's Note: “Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors” [Appl. Phys. Lett. 123, 262107 (2023)

Publisher's Note: “Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors” [Appl. Phys. Lett. <b>123</b>, 262107 (2023)

Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(&amp;lt;6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (&amp;gt;108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K.

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

Interface state analysis of Schottky-gated p-AlGaN/u-GaN/AlGaN p-FET with negligible hysteresis at high temperatures

In this Letter, we demonstrate the Schottky gated p-AlGaN/u-GaN/AlGaN p-channel field-effect transistors (p-FETs) with an extremely low interface state density of 2.5 × 1011 cm−2 eV−1. Benefiting from the high-quality Schottky interface with suppressed interface states, the excellent stability with negligible hysteresis is proved, even after ten sequential dual I–V sweeps at 150 °C. Meanwhile, the trap density, confirmed by the temperature-dependent conductance method, is still below 1012 cm−2 eV−1 at high temperature. Furthermore, the fabricated p-AlGaN/u-GaN/AlGaN p-FET with a gate to drain distance of 1.8 μm shows a breakdown voltage of −128 V and an effective on-resistance of 7.2 kΩ mm, which allows the further scale down in terms of the source–drain spacing to improve the conduction current for low voltage application. The ultra-stable I–V characteristics of the fabricated Schottky-gated p-AlGaN/u-GaN/AlGaN p-FETs show great potential for next-generation integrated circuit application at high temperatures.

Coherence Improvement of Dual-Lens Electron Holography

Abstract Coherence is one of the limiting factors in off-axis electron holography applications. This paper reports methods to improve coherence ∼18-fold by using a smaller biprism and implementing a direct electron counting camera (K-camera) in combination with an imaging filter system. We achieved 0.4 nm fringe spacing with a 1.5 μm field-of-view and ∼33% fringe contrast. The maximum coherence number, N′, of ∼1.8 × 103 was achieved, where N′ is defined as the number of fringes times fringe contrast. High spatial resolution junction profile images (nm scale) of n-channel and p-channel field-effect transistors (nFET and pFET) are demonstrated with a large field-of-view (μm scale).

Non-volatile tuning of normally-on and off states of deep depletion ZrO2/O-terminated high voltage diamond MOSFET

Based on the stability of the deep depletion regime in diamond and the outstanding properties of this promising material for its use in power devices, p-channel deep depletion metal oxide semiconductor field effect transistors were fabricated on a (001) Ib nitrogen-doped high pressure high temperature diamond substrate. Taking advantage of the new concept of the non-volatile diamond-based photo switch, it is demonstrated that it is possible to tune the normally-on and normally-off states of the transistor by configuring the pn-junction space charge region. The devices under study was designed following an interdigital-like and a circular-like architectures presenting low threshold voltages (between 3 V and −3 V), an on/off ratio of 107 and a critical electric field numerically assessed of 9 MV.cm−1 at room temperature. This new degree of freedom opens the route for diamond based power electronics.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

In thiswork, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2 O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2 . An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Electrochemically exfoliated phosphorene nanosheet thin films for wafer-scale near-infrared phototransistor array

Two-dimensional (2D) black phosphorus (BP), or phosphorene, has recently emerged as a promising 2D semiconductor because of its p-type charge transport behavior and near-infrared photoresponsivity. However, the application of BP in practical electronic and optoelectronic devices is hindered by challenges in producing high-quality BP films over large areas. In this manuscript, we present a facile solution-based process to create wafer-scale BP films for fabrication of p-channel field-effect transistors that are responsive to near infrared light. Few-layer BP nanosheets are first exfoliated from the bulk crystal via electrochemical intercalation of cationic molecules and then vacuum-filtered through an anodic aluminum oxide membrane. The resulting BP film can be transferred onto an SiO2-coated silicon substrate, thereby allowing for realization of field-effect transistors after electrode deposition and thermal annealing. The transistor array exhibits spatial uniformity in electrical performance with an average hole mobility of ~0.002 cm2 V−1 s−1 and on/off ratio of 130. Furthermore, gate-induced modulation of the BP channel allows for enhancement in the photoresponsivity for 1550-nm light illumination up to 24 mA W−1, which benefits the application of the phototransistor array for near infrared imaging.

Demonstration of Acceptor-Like Traps at Positive Polarization Interfaces in Ga-Polar P-type (AlGaN/AlN)/GaN Superlattices

The shortcomings with acceptors in p-type III-nitride semiconductors have resulted in not many efforts being presented on III-nitride based p-channel electronic devices (here, field effect transistors (FETs)). The polarization effects in III-nitride superlattices (SLs) lead to the periodic oscillation of the energy bands, exhibiting enhanced ionization of the deep acceptors (Mg in this study), and hence their use in III-nitride semiconductor-based light-emitting diodes (LEDs) and p-channel FETs is beneficial. This study experimentally demonstrates the presence of acceptor-like traps at the positive polarization interfaces acting as the primary source of holes in Ga-polar p-type uniformly doped (AlGaN/AlN)/GaN SLs with limited Mg doping. The observed concentration of holes exceeding that of the dopants incorporated into the samples during growth can be attributed to the ionization of acceptor-like traps, located at 0.8 eV above the valence band of GaN, at positive polarization interfaces. All samples were grown using the metal organic vapor phase epitaxy (MOVPE) technique, and the materials’ characterization was carried out using X-ray diffraction and Hall effect measurements. The hole concentrations experimentally measured are juxtaposed with the calculated value of hole concentrations from FETIS®, and the measured trends in mobility are explained using the amplitude of separation of the two-dimensional hole gas in the systems from the positive polarization interfaces.

Analysis of Low-Frequency 1/f Noise Characteristics for MoTe2 Ambipolar Field-Effect Transistors.

Low-frequency electronic noise is an important parameter used for the electronic and sensing applications of transistors. Here, we performed a systematic study on the low-frequency noise mechanism for both p-channel and n-channel MoTe2 field-effect transistors (FET) at different temperatures, finding that low-frequency noise for both p-type and n-type conduction in MoTe2 devices come from the variable range hopping (VRH) transport process where carrier number fluctuations (CNF) occur. This process results in the broad distribution of the waiting time of the carriers between successive hops, causing the noise to increase as the temperature decreases. Moreover, we found the noise magnitude for p-type MoTe2 FET hardly changed after exposure to the ambient conditions, whereas for n-FET, the magnitude increased by nearly one order. These noise characteristics may provide useful guidelines for developing high-performance electronics based on the emerging transition metal dichalcogenides.

Operational experience of the Belle II pixel detector

The Belle II experiment at the SuperKEKB accelerator has started its physics data taking with the full detector setup in March 2019. It aims to collect 40 times more e+e− collision data compared with its predecessor Belle experiment. The Belle II pixel detector (PXD) is based on the Depleted P-channel Field Effect Transistor (DEPFET) technology. The PXD plays an important role in the tracking and vertexing of the Belle II detector. Its two layers are arranged at radii of 14 mm and 22 mm around the interaction point. The sensors are thinned down to 75 μm to minimize multiple scattering, and each module has interconnects and ASICs integrated on the sensor with silicon frames for mechanical support. PXD showed good performance during data taking. It also faces several operational challenges due to the high background level from the SuperKEKB accelerator, such as the damage from beam loss events, the drift in the HV working point due to radiation effect, and the impact of the high background.

Boosting the Sensitivity of the Nanopore Field-Effect Transistor to Translocating Single Molecules

Nano-scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) is exploited to benefit the interdisciplinary field of single-molecule biosensing. While single-molecule DNA sequencing is done successfully by ionic current sensing through nanopores, the unambiguous characterization of more complex single biomolecules, such as fast translocating proteins, remains challenging with existing techniques. However, the nanopore-FET (NP-FET), a device with a nanopore embedded within the channel of the FET, is a promising new device detecting the motion of a molecule through the nanopore based on the transistor’s electronic current. This nano-scale FET-based approach enables next-generation single-molecule sensing by offering larger signals and hence higher bandwidth, responding to a key challenge of detecting fast translocating molecules, and by offering denser electronic system packing and therefore more parallel sensing. However, the sensitivity of the nanopore-FET reported so far was limited to about 30%. In this paper, we show that the inherent potential of this hybrid nanofluidic-nanoelectronic device significantly exceeds the initial reportings by demonstrating sensitivity predictions up to 1000%. Our findings are supported with 3D nanofluidic-nanoelectronic open-source device simulations. Insight in the versatility of the device is provided through geometrical device optimization and demonstration that the device is sensitive to both positively and negatively charged molecules in both n- and p-channel FET configurations. These promising features, together with the immense expertise in MOS fabrication and scaling, offer a path to a highly parallelized and scalable sensor platform for genomics and proteomics.

An enhanced two-dimensional hole gas (2DHG) C\u2013H diamond with positive surface charge model for advanced normally-off MOSFET devices

Though the complementary power field effect transistors (FETs), e.g., metal–oxide–semiconductor-FETs (MOSFETs) based on wide bandgap materials, enable low switching losses and on-resistance, p-channel FETs are not feasible in any wide bandgap material other than diamond. In this paper, we propose the first work to investigate the impact of fixed positive surface charge density on achieving normally-off and controlling threshold voltage operation obtained on p-channel two-dimensional hole gas (2DHG) hydrogen-terminated (C-H) diamond FET using nitrogen doping in the diamond substrate. In general, a p-channel diamond MOSFET demonstrates the normally-on operation, but the normally-off operation is also a critical requirement of the feasible electronic power devices in terms of safety operation. The characteristics of the C–H diamond MOSFET have been analyzed with the two demonstrated charge sheet models using the two-dimensional Silvaco Atlas TCAD. It shows that the fixed-Fermi level in the bulk diamond is 1.7 eV (donor level) from the conduction band minimum. However, the upward band bending has been obtained at Al2O3/SiO2/C-H diamond interface indicating the presence of inversion layer without gate voltage. The fixed negative charge model exhibits a strong inversion layer for normally-on FET operation, while the fixed positive charge model shows a weak inversion for normally-off operation. The maximum current density of a fixed positive interface charge model of the Al2O3/C-H diamond device is − 290 mA/mm, which corresponds to that of expermental result of Al2O3/SiO2/C-H diamond − 305 mA/mm at a gate-source voltage of − 40 V. Also, the threshold voltage Vth is relatively high at Vth = − 3.5 V, i.e., the positive charge model can reproduce the normally-off operation. Moreover, we also demonstrate that the Vth and transconductance gm correspond to those of the experimental work.

Investigation of Ge-Based P-Channel Planar-Doped Barrier FETs integrated on Si

Ge-based p-channel Field-Effect Transistors (FETs) are regarded as the most promising devices to replace Si-based p-channel FETs with emphasis on reducing device power-consumption. Planar-Doped Barrier FETs (PDBFETs) are considered good candidates for tuning Ge-based FETs performance: with channels almost undoped except for a very thin region, creating necessary barrier for operation. PDBFETs enables inspection of behaviour with carriers away from surface, experiencing bulk properties. The aim of this work is to show the capability of the PDBFET concept to improve the performance of Ge-based devices even on large scaled device. Applying the concept of channel doping modulation to Ge-based FETs is demonstrated through fabrication and electrical characterization of Ge-based p-PDBFETs with optimistic results achieving off-state currents of sub-nA/μm even with relatively large sized devices, which are competitive in electrostatic performance to scaled, more complicated design devices. Sources of leakage current are considered through improving surface treatment. Applying low temperature measurements elaborated the possibility of higher performance with dimension scaling availability.

Insight into interface electrical properties of metal–oxide–semiconductor structures fabricated on Mg-implanted GaN activated by ultra-high-pressure annealing

GaN-based metal–oxide–semiconductor (MOS) devices, such as n- and p-type capacitors and inversion- and accumulation-type p-channel field effect transistors (MOSFETs), were fabricated by Mg-ion implantation and ultra-high-pressure annealing (UHPA) under 1-GPa nitrogen pressure. Even though UHPA was conducted at 1400 °C without protective layers on GaN surfaces, n-type MOS capacitors with SiO2 gate dielectrics formed on non-ion-implanted regions exhibited well-behaved capacitance–voltage characteristics with negligible hysteresis and frequency dispersion, indicating distinct impact of UHPA in suppressing surface degradation during high-temperature annealing. Efficient activation of the implanted Mg dopants and reasonable hole accumulation at the SiO2/GaN interfaces were also achieved for p-type capacitors by UHPA, but the fabricated inversion- and accumulation-type p-channel GaN MOSFETs were hardly turned on. The findings reveal extremely low hole mobility at GaN MOS interfaces and suggest an intrinsic obstacle for the development of GaN-based MOS devices.

Characterization of Electrical Properties of Suspended ZnO Nanowires Using a Nanorobotic Manipulation System Inside a Scanning Electron Microscope for Nanoelectronic Applications

Electrical characterization of semiconducting oxide nanowires (NWs) is mostly performed using complex techniques, which necessitates a series of costly nanofabrication procedures. In this work, with the aim to provide a low-cost, feasible, facile, and reproducible approach for enabling the study of NW electrical properties, we report direct electrical measurements on individual and overlapped suspended zinc oxide NWs (ZnO NWs). We have succeeded in constructing both two- and three-terminal devices simply by employing tungsten (W) nanoprobes with the aid of a nanomanipulation system embedded inside a scanning electron microscope’s vacuum chamber. Stable contacts were established using the Joule heating effect and e-beam exposure at the junctions between the NW and the pre-cleaned W tips. P-channel field-effect transistor devices were achieved with an on–off current ratio of ∼101, a threshold voltage (>1.5 V), a transconductance of ∼16 μS, a sub-threshold swing of ∼220 mV/decade, and field-effect carrier mobility roughly estimated to be around 926.4 cm2/(V·s) after correction for contact resistances/optimization. The average resistivity of ZnO NWs was calculated to be ∼2.23 × 10–2 Ω·cm for NWs with diameters between 70 and 500 nm. Besides, we have demonstrated a contact resistance of ∼19.60 kΩ and a Schottky barrier height of ∼0.37 eV present at W/ZnO NW interfaces. The contact resistance between two overlapped ZnO NWs was estimated to be ∼283 kΩ, which is relatively higher than that offered between W/ZnO NWs. This work provides a solid experimental procedure to address true intrinsic electrical properties at metal/semiconductor interfaces, and our findings have potential applications in next-generation 3D suspended ZnO NW-based nanoelectronic devices.

Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride (GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules. Recently emerging GaN-based p-channel field-effect transistors (FETs) and monolithic integration techniques enable the implementation of GaN-based complementary logic (CL) circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functionality. In this article, holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems, based on the material limit of GaN and state-of-the-art experimental results. It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform could be as short as sub-nanosecond, which sufficiently satisfies the requirement of power conversion systems typically with operating frequencies less than 10 MHz. With the currently adopted n-FET-based logic gates (e.g., directly coupled FET logic) replaced by CL gates, the power consumption of peripheral logic circuits could be substantially suppressed by more than 103 times, mainly due to the elimination of the pronounced static power loss. Consequently, the energy efficiency of the entire system could be substantially improved.

Hot-Electron-Induced Punch-Through (HEIP) Effect in p-MOSFET Enhanced by Mechanical Stress

Hot-carrier-induced degradation of short p-channel field-effect transistors in the presence of externally applied vertical mechanical force is investigated. The mechanical stress was induced in the devices by applying a normal load with a nanoindenter. Using finite element modeling, the induced stress to the channel was estimated to reach GPa range. It is shown that compressive mechanical stress considerably enhances the impact ionization rate and the generation of secondary electron-hole pairs. These can be trapped in the gate oxide and cause a hot-electron-induced punch-through effect and effective p-channel length reduction even after both mechanical and electrical stresses are removed. The presented findings indicate the importance of mechanical stress control and engineering for improving the device reliability.

Demonstration of 4H-SiC CMOS circuits consisting of well-balanced n- and p-channel MOSFETs fabricated by ultrahigh-temperature gate oxidation

Complementary metal-oxide-semiconductor inverters featuring steep voltage-transfer characteristics (VTC) were successfully fabricated on 4H-SiC(0001) substrates. Even without nitridation of the MOS interfaces, well-balanced n- and p-channel field-effect transistors were realized by means of ultrahigh-temperature gate oxidation (HTO) at 1600 °C under reduced oxygen partial pressure. Improvements in the performances of both n- and p-channel SiC metal-oxide-semiconductor field-effect transistors were achieved by subsequently performing forming gas annealing (FGA) at 1200 °C, leading to mostly symmetric VTC with negligible hysteresis. The effect of HTO and subsequent FGA at high temperatures was verified from the stable and improved performance of 23-stage ring oscillators over a wide temperature range.