Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

Taikyu Kim,Seungwu Han,Jae Kyeong Jeong,Pilgyu Byeon,Aeran Song,Sung-Yoon Chung,Cheol Hee Choi,Miso Lee,Kwon-Shik Park,Kwun-Bum Chung

doi:10.1038/s41699-021-00280-7

Abstract

Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Highlights

The classical two-dimensional (2D) downscaling of Si semiconductors on the basis of Dennard’s design principle is reaching the fundamental physical limits
N-channel IGZO field-effect transistors (FETs) have been limited to the niche application of low power/frequency electronics, such as display technology, due to the lack of p-type dopability arising from the strong oxygen 2p orbital localization
The hexagonal crystalline structure was confirmed by X-ray diffraction (XRD) analysis of polycrystalline Te films deposited by magnetron sputtering at room temperature

Summary

Introduction

The classical two-dimensional (2D) downscaling of Si semiconductors on the basis of Dennard’s design principle is reaching the fundamental physical limits. An alumina (Al2O3) encapsulation layer significantly assists the growth of the underlying hexagonal Te crystal through interfacial energy stabilization and enlarges the the Gibbs formation energy for Al2O3 is far lower than that for TeO230, suggesting conversion from a mixture of Te and TeO2 to homogeneous polycrystalline Te. crystal size in the sputtered Te film, leading to a very large enhancement in the performance of FETs. The resulting CMOS inverter based on this encapsulated p-channel crystalline Te and an n-channel IGZO layer exhibits great rail-to-rail swing with high gain and noise margins.

Results

Conclusion