P-channel Field Effect Transistors Research Articles

Improvement of P-Type Contact in WSe2 Field-Effect Transistors via Defect Engineering.

Two-dimensional (2D) material-based p-channel field-effect transistors (FETs) are key elements for the realization of complementary metal-oxide-semiconductor (CMOS) technology. WSe2, as the primary material for p-channel FETs, is suffering from intrinsic atomic defects and extrinsic defects during metal deposition, making it difficult to form high-quality metal-semiconductor contact interfaces. This leaves significant space for improvement in the performance of p-channel FETs. In this work, we propose an effective defect optimization strategy, focusing on the contact interface. The trifluoromethyl thianthrenium triflate (TTT) molecule treatment on WSe2 increases the hole density, induces the defect passivation, and enhances the hole transport efficiency. The high work-function semimetal TiS2 effectively prevents damage caused by metal deposition and facilitates efficient hole transport. The optimized WSe2-CF3-TiS2 FET achieves a high hole mobility of ∼147 cm2/V·s and demonstrates excellent stability at 200 °C.

Complementary Circuits with WSe2/Organic Semiconductor Heterostructure Field-Effect Transistors.

A device architecture based on heterostructure WSe2/organic semiconductor field-effect transistors (FETs) is demonstrated in which ambipolar conduction is virtually eliminated, resulting in essentially unipolar FETs realized from an ambipolar semiconductor. For p-channel FETs, an electron-accepting organic semiconductor such as hexadecafluorocopperphthalocyanine (F16CuPc) is used to form a heterolayer on top of WSe2 to effectively trap any undesirable electron currents. For n-channel FETs, a hole-accepting organic semiconductor such as pentacene is used to reduce the hole currents without affecting the electron currents. Off-currents are reduced in FETs with heterolayers compared to WSe2 FETs without organic heterolayers, which will decrease static power dissipation in complementary circuits. In all FETs reported in this work, the organic heterolayers cover only part of the channel, which results in more effective trapping of the carrier type that must be reduced. This device design approach can be effectively combined with p-type doping and contact metal engineering to improve WSe2 based FETs and circuits. Complementary inverters realized with such heterostructured FETs exhibit excellent transfer characteristics. This design approach is also applicable to other ambipolar semiconductors besides WSe2.

Improved threshold voltage stability for GaN p-channel field effect transistors by hydrogen plasma treatment

Improved threshold voltage stability for GaN p-channel field effect transistors by hydrogen plasma treatment

Carrier Tunnelings on Ultrashort‐Gate Junction‐Less Field‐Effect Transistor Designs

This study discusses tunneling problems encountered when designing ultrashort‐gate junction‐less field‐effect transistors (FETs). Ultrathin‐body silicon‐on‐insulator (UTB‐SOI) FETs are suitable for nano‐length gate designs owing to the augmented bandgap at channel regions. However, a comprehensive understanding of source‐to‐drain (S/D) and gate‐dielectric (G/D) tunneling is essential to ensure optimal performance and reliability. In this study, numerical simulations of UTB‐SOI FETs are conducted to reveal their effects. First, for S/D tunneling, only a p‐channel FET (PFET) is considered critical, and larger tunneling mass eases this problem. Second, for G/D tunneling, an n‐channel FET (NFET) is considered critical. Therefore, the oxide‐wall UTB‐SOI design is considered for the NFET, enabling a large and small ratios for NFET and PFET. Conversely, the conventional trenched UTB‐SOI is considered suitable for PFET. Moreover, the findings demonstrate that adopting hafnium oxide (HfO) as the oxide material renders good FET characteristics. The optimized FET designs can facilitate the minimum gate length to be 1 nm or shorter, especially for NFETs.

High mobility p-channel GaN heterostructures grown by MOCVD through impurity engineering

The p-GaN/AlGaN/GaN heterostructures with integrated n-channel and p-channel have been extensively applied in p-channel field effect transistor (p-FET) devices and complementary (CMOS) logic circuits. However, the hole mobility of the p-channel is still low, especially in the heterostructures grown by metalorganic chemical vapor deposition (MOCVD). In this work, an impurity engineering was designed by introducing Ga vacancies in the p-channel, so that the diffused Mg impurity could substitute the Ga site and form MgGa−1 rather than Mginter+2. The charged impurity scattering was hence suppressed due to the reduction of the impurity charge. As a result, the GaN heterostructure with a hole mobility of 21.8 cm2/V·s with a sheet hole density of 1.02 × 1013/cm2 was realized at room temperature by MOCVD. This work paves a way for improving the transport properties of GaN heterostructures and lays a foundation of high performance GaN-based p-FET devices and CMOS logic circuits on Si substrates.

Tunable Charge Transport Using Heterocycles-Flanked Alkoxyphenanthrenes for High-Performing OFETs.

A series of new heterocycles-flanked alkoxyphenanthrenes with D'-D-D' and A-D-A architecture was synthesized for high-performance solution-processable p-channel, n-channel, and ambipolar organic field-effect transistors. The impact of electron-donating and -accepting abilities of the sulfur- and nitrogen-containing heteroaromatics on photophysical, electrochemical, and semiconducting properties was analyzed. The presence of heteroaryl rings improves the extended conjugation, two-dimensional lattices of π-π stacks, and increased molecular interaction of the functionalized phenanthrenes (PN) to allow better self-assembly. The electronically dynamic PN self-assembles into continuous microdomains, forming percolation channels for holes, electrons, or both reliant on functionalization. The low-lying LUMO levels of the compounds enabled ambipolar transport and reduced energy levels for charge injections. Spin-coated devices fabricated using functionalized PN with sulfur-containing heteroaryl substituted PN exhibited the highest hole mobility of 0.85 cm2/(V s) with 108 on/off current ratio. Compounds with A-D-A architecture showed n-channel/ambipolar charge transport, especially napthalimide acceptor substituted PN exhibited n-channel electron mobility of 0.78 cm2/(V s) and an on/off ratio of 106. X-ray diffraction and scanning electron microscopy studies further delineate the impact of efficient packing in the film. Quantum chemistry calculations combined with Marcus-Hush electron transfer theory interpret the transport parameters, and heteroatoms are established to impact the charge mobility intensely.

Heterostructure WSe2/copper hexadecafluorophthalocyanine (F16CuPc) field-effect transistors for efficient suppression of electron transport

The use of the organic semiconductor copper hexadecafluorophthalocyanine (F16CuPc) in WSe2 based heterostructure field-effect transistors (FETs) is shown to result in a large reduction in electron current while not significantly impacting the hole current. This approach is promising for use in p-channel FETs in which electron transport is undesirable and increases leakage currents and power dissipation in the off-state. The reduction in on-state electron currents, by up to three orders of magnitude, is due to the transfer of electrons to the low-mobility states in F16CuPc due to the greater electron affinity of the organic semiconductor compared to WSe2. The off-state currents under a drain bias are reduced by more than four orders of magnitude due to the effective suppression of electron currents. This is a result of the formation of type II heterostructure between F16CuPc and WSe2. Electrons in this heterostructure FET will preferentially transfer to F16CuPc, while holes will tend to remain in the high mobility WSe2 layer. This effect is more marked in monolayer WSe2 based FETs compared to multilayer WSe2 FETs due to a larger difference in electron affinities with respect to F16CuPc. Also, the magnitude of electron current suppression was further enhanced when F16CuPc is deposited only on a part of the channel near the source of WSe2 +F16CuPc FETs.

Experimental qualification and modelling of the non-linear response of the DEPFET active pixel sensor for the DSSC camera

A modified Depleted P-Channel Field Effect Transistor (DEPFET) is the key feature of the DEPFET Sensor with Signal Compression (DSSC), a 1 Mpixel X-ray camera aiming at ultra-fast imaging of soft X-rays at the European XFEL. Operation of large-area devices with a large number of DSSC-type DEPFET pixels requires the accurate knowledge of the sensitivity of the response to the relevant DEPFET parameters. The paper presents the experimental qualification of the response of DSSC-type DEPFET pixels in the space of 4 relevant parameters: drain current, source voltage, drain voltage and back side voltage. The obtained results allow estimation of the impact of the inevitable parameter fluctuations in large monolithic sensors and of the actual trimming range of the shape of signal compression in view of the pixelwise calibration of the 1 Mpixel DSSC camera.

Design of low delay low power hybrid logic based flip-flop using FinFET

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

Publisher's Note: “Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors” [Appl. Phys. Lett. 123, 262107 (2023)

Publisher's Note: “Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors” [Appl. Phys. Lett. <b>123</b>, 262107 (2023)

Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(&amp;lt;6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (&amp;gt;108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K.

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

Interface state analysis of Schottky-gated p-AlGaN/u-GaN/AlGaN p-FET with negligible hysteresis at high temperatures

In this Letter, we demonstrate the Schottky gated p-AlGaN/u-GaN/AlGaN p-channel field-effect transistors (p-FETs) with an extremely low interface state density of 2.5 × 1011 cm−2 eV−1. Benefiting from the high-quality Schottky interface with suppressed interface states, the excellent stability with negligible hysteresis is proved, even after ten sequential dual I–V sweeps at 150 °C. Meanwhile, the trap density, confirmed by the temperature-dependent conductance method, is still below 1012 cm−2 eV−1 at high temperature. Furthermore, the fabricated p-AlGaN/u-GaN/AlGaN p-FET with a gate to drain distance of 1.8 μm shows a breakdown voltage of −128 V and an effective on-resistance of 7.2 kΩ mm, which allows the further scale down in terms of the source–drain spacing to improve the conduction current for low voltage application. The ultra-stable I–V characteristics of the fabricated Schottky-gated p-AlGaN/u-GaN/AlGaN p-FETs show great potential for next-generation integrated circuit application at high temperatures.

Coherence Improvement of Dual-Lens Electron Holography

Abstract Coherence is one of the limiting factors in off-axis electron holography applications. This paper reports methods to improve coherence ∼18-fold by using a smaller biprism and implementing a direct electron counting camera (K-camera) in combination with an imaging filter system. We achieved 0.4 nm fringe spacing with a 1.5 μm field-of-view and ∼33% fringe contrast. The maximum coherence number, N′, of ∼1.8 × 103 was achieved, where N′ is defined as the number of fringes times fringe contrast. High spatial resolution junction profile images (nm scale) of n-channel and p-channel field-effect transistors (nFET and pFET) are demonstrated with a large field-of-view (μm scale).

Non-volatile tuning of normally-on and off states of deep depletion ZrO2/O-terminated high voltage diamond MOSFET

Based on the stability of the deep depletion regime in diamond and the outstanding properties of this promising material for its use in power devices, p-channel deep depletion metal oxide semiconductor field effect transistors were fabricated on a (001) Ib nitrogen-doped high pressure high temperature diamond substrate. Taking advantage of the new concept of the non-volatile diamond-based photo switch, it is demonstrated that it is possible to tune the normally-on and normally-off states of the transistor by configuring the pn-junction space charge region. The devices under study was designed following an interdigital-like and a circular-like architectures presenting low threshold voltages (between 3 V and −3 V), an on/off ratio of 107 and a critical electric field numerically assessed of 9 MV.cm−1 at room temperature. This new degree of freedom opens the route for diamond based power electronics.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

In thiswork, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2 O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2 . An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Electrochemically exfoliated phosphorene nanosheet thin films for wafer-scale near-infrared phototransistor array

Two-dimensional (2D) black phosphorus (BP), or phosphorene, has recently emerged as a promising 2D semiconductor because of its p-type charge transport behavior and near-infrared photoresponsivity. However, the application of BP in practical electronic and optoelectronic devices is hindered by challenges in producing high-quality BP films over large areas. In this manuscript, we present a facile solution-based process to create wafer-scale BP films for fabrication of p-channel field-effect transistors that are responsive to near infrared light. Few-layer BP nanosheets are first exfoliated from the bulk crystal via electrochemical intercalation of cationic molecules and then vacuum-filtered through an anodic aluminum oxide membrane. The resulting BP film can be transferred onto an SiO2-coated silicon substrate, thereby allowing for realization of field-effect transistors after electrode deposition and thermal annealing. The transistor array exhibits spatial uniformity in electrical performance with an average hole mobility of ~0.002 cm2 V−1 s−1 and on/off ratio of 130. Furthermore, gate-induced modulation of the BP channel allows for enhancement in the photoresponsivity for 1550-nm light illumination up to 24 mA W−1, which benefits the application of the phototransistor array for near infrared imaging.

Demonstration of Acceptor-Like Traps at Positive Polarization Interfaces in Ga-Polar P-type (AlGaN/AlN)/GaN Superlattices

The shortcomings with acceptors in p-type III-nitride semiconductors have resulted in not many efforts being presented on III-nitride based p-channel electronic devices (here, field effect transistors (FETs)). The polarization effects in III-nitride superlattices (SLs) lead to the periodic oscillation of the energy bands, exhibiting enhanced ionization of the deep acceptors (Mg in this study), and hence their use in III-nitride semiconductor-based light-emitting diodes (LEDs) and p-channel FETs is beneficial. This study experimentally demonstrates the presence of acceptor-like traps at the positive polarization interfaces acting as the primary source of holes in Ga-polar p-type uniformly doped (AlGaN/AlN)/GaN SLs with limited Mg doping. The observed concentration of holes exceeding that of the dopants incorporated into the samples during growth can be attributed to the ionization of acceptor-like traps, located at 0.8 eV above the valence band of GaN, at positive polarization interfaces. All samples were grown using the metal organic vapor phase epitaxy (MOVPE) technique, and the materials’ characterization was carried out using X-ray diffraction and Hall effect measurements. The hole concentrations experimentally measured are juxtaposed with the calculated value of hole concentrations from FETIS®, and the measured trends in mobility are explained using the amplitude of separation of the two-dimensional hole gas in the systems from the positive polarization interfaces.

Analysis of Low-Frequency 1/f Noise Characteristics for MoTe2 Ambipolar Field-Effect Transistors.

Low-frequency electronic noise is an important parameter used for the electronic and sensing applications of transistors. Here, we performed a systematic study on the low-frequency noise mechanism for both p-channel and n-channel MoTe2 field-effect transistors (FET) at different temperatures, finding that low-frequency noise for both p-type and n-type conduction in MoTe2 devices come from the variable range hopping (VRH) transport process where carrier number fluctuations (CNF) occur. This process results in the broad distribution of the waiting time of the carriers between successive hops, causing the noise to increase as the temperature decreases. Moreover, we found the noise magnitude for p-type MoTe2 FET hardly changed after exposure to the ambient conditions, whereas for n-FET, the magnitude increased by nearly one order. These noise characteristics may provide useful guidelines for developing high-performance electronics based on the emerging transition metal dichalcogenides.

Operational experience of the Belle II pixel detector

The Belle II experiment at the SuperKEKB accelerator has started its physics data taking with the full detector setup in March 2019. It aims to collect 40 times more e+e− collision data compared with its predecessor Belle experiment. The Belle II pixel detector (PXD) is based on the Depleted P-channel Field Effect Transistor (DEPFET) technology. The PXD plays an important role in the tracking and vertexing of the Belle II detector. Its two layers are arranged at radii of 14 mm and 22 mm around the interaction point. The sensors are thinned down to 75 μm to minimize multiple scattering, and each module has interconnects and ASICs integrated on the sensor with silicon frames for mechanical support. PXD showed good performance during data taking. It also faces several operational challenges due to the high background level from the SuperKEKB accelerator, such as the damage from beam loss events, the drift in the HV working point due to radiation effect, and the impact of the high background.