Oxide Thickness Fluctuations Research Articles

Variability analysis of the epitaxial layer TFET due to gate work function variation, random dopant fluctuation, and oxide thickness fluctuation using the statistical impedance field method

In this paper, a comparative study on process variability considering work function variation (WFV), random dopant fluctuation (RDF), and oxide thickness fluctuation (OTF) in epitaxial layer tunnel field effect transistor (TFET) with SiGe source (SiGe-ETLTFET) is statistically analyzed using impedance field method (IFM) in Santaurus TCAD tool. Effect of different grain sizes of the gate metal and other device parameter scaling on the variability source are investigated by evaluating the standard deviation of threshold voltage (V th), on current (I ON), and off current (I OFF). At smaller AverageGrainSize, the dispersions in electrical parameters are close to normal, whereas for large AverageGrainSize dispersion increases and deviates from the normal distribution. Compared to RDF and WFV, OTF is not a significant cause of variability in SiGe-ETLTFET. It is found that RDF is the most sensitive variability source while device scaling is concerned. Moreover, L ov scaling causes the most acute fluctuation of electrical parameters for all considered variability sources. The slope of the Pelgrom plot, A VT, of SiGe-ETLTFET considering all variability sources, is smaller than the already reported values for the FinFET and MOSFET.

Investigation of statistical variability in non-uniformly doped bulk junctionless FinFET

The impact of random dopant fluctuation (RDF), work function variation (WFV) and oxide thickness fluctuation (OTF) on the statistical variability of the electrical performance of non-uniformly doped bulk junctionless (JL) FinFET has been studied using three dimensional TCAD simulations. We illustrate that by specifying the appropriate doping profile in the bulk JL FinFET, enhanced statistical variability and electrical characteristics can be achieved. Numerically, it is indicated by values of standard deviation of device parameters, that the performance parameters of a uniformly doped bulk JL FinFET are seriously influenced by statistical variation compared to its non-uniformly doped counterparts.

A Novel Approach to Analysis of F-N Tunneling Characteristics in MOS Capacitor Having Oxide Thickness Fluctuation

The new indicators, effective gate oxide thickness tc and effective gate electrode area D, and their combination are applied for a new analysis method of Fowler-Nordheim (F-N) tunneling characteristics in MOS capacitor having oxide thickness fluctuation. This method considering the conduction properties of F-N tunneling characteristics correlates its characteristics to the oxide reliability. These indicators quantified with the influence of the oxide thickness fluctuation can provide the net values of the electric field and the current density on the gate oxide. This new analysis method will lead to reducing the evaluation time for the reliability assessment.

Oxidation of step edges on vicinal 4H-SiC(0001) surfaces

The oxidation processes of stepped SiC(0001) surfaces are studied within the ab initio atomistic thermodynamics approach. Our calculations show that a one-dimensional -Si-O- chain structure as a precursor for oxide growth on stepped SiC surfaces is formed along the step edge, promoting further oxidation of the step edges. Following the modified Deal-Grove oxidation model, we also find that the oxidation rate at steps is higher than that at terraces by three orders of magnitude. These findings give a reasonable explanation for the oxide thickness fluctuation between the step and the terrace observed in the previous experiments.

Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

Ultimate scaling of TiN/ZrO2/TiN capacitors: Leakage currents and limitations due to electrode roughness

In this paper, we investigate the influence of electrode roughness on the leakage current in TiN/high-κ ZrO2/TiN (TZT) thin-film capacitors which are used in dynamic random access memory cells. Based on a microscopic transport model, which is expanded to incorporate electrode roughness, we assess the ultimate scaling potential of TZT capacitors in terms of equivalent oxide thickness, film smoothness, thickness fluctuations, defect density and distribution, and conduction band offset (CBO). The model is based on three-dimensional, fully self-consistent, kinetic Monte Carlo transport simulations. Tunneling transport in the bandgap of the dielectric is treated, which includes defect-assisted transport mechanisms. Electrode roughness is described in the framework of fractal geometry. While the short-range roughness of the electrodes is found not to influence significantly the leakage current, thickness fluctuations of the dielectric have a major impact. For thinner dielectric films they cause a transformation of the dominant transport mechanism from Poole–Frenkel conduction to trap-assisted tunneling. Consequently, the sensitivity of the leakage current on electrode roughness drastically increases on downscaling. Based on the simulations, optimization of the CBO is suggested as the most viable strategy to extend the scalability of TZT capacitors over the next chip generations.

Direct Tunnelling Gate Leakage Variability in Nano-CMOS Transistors

A comprehensive simulation methodology for the systematic study of gate leakage variability in realistic nanoscale bulk CMOS transistors, on a statistical scale, is presented for the first time. This is based on the Glasgow “atomistic” 3-D drift-diffusion device simulator with density-gradient quantum corrections, which is capable of modeling various sources of stochastic variability, including random dopant fluctuations (RDFs) and oxide thickness fluctuations (OTFs). The capabilities of the simulator are extended to model direct tunnelling of electrons through the gate dielectric by means of an improved Wentzel-Kramer-Brillouin approximation with one model parameter only. The methodology is applied for the detailed study of the gate leakage variability arising from RDFs and OTFs in a 25-nm square-gate n-channel metal-oxide-semiconductor field-effect transistor with conventional architecture. The origins of gate leakage variability and gate current increase due to RDFs and OTFs individually, and in combination, are analyzed for bias conditions that are relevant to static power dissipation in digital CMOS circuits.

Random variability modeling and its impact on scaled CMOS circuits

Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V th ) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design.

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Threshold voltage (Vth) variations induced by oxide thickness fluctuation (OTF) and local gate depletion (LGD) in metal–oxide–semiconductor field-effect transistors (MOSFETs) are studied using classical three-dimensional (3D) drift-diffusion (DD) simulations. The models for both OTF and LGD are based on transmission electron microscopy (TEM) observations. OTF is generated by random roughness steps at a SiO2/Si interface and LGD is generated by the random size and position of grains in a polycrystalline silicon (poly-Si) gate. The impact of both models on Vth variation and its distribution are investigated and compared with measured data. The Takeuchi coefficient BVT is used to analyze Vth variation. It is found that, although both OTF and LGD have an impact on Vth variation, their influences are small in terms of BVT value, the dependence of BVT on Na and Tinv, and the Vth distribution.

Surface roughness induced device variability: 3D ab initio Monte Carlo simulation study

It is expected that published results from drift diffusion simulation of oxide thickness fluctuations in nano-scale devices underestimates the true intrinsic device parameter variation by neglecting local variations in surface roughness scattering. We present initial results from 3D ‘bulk’ Monte Carlo simulation including an ab initio treatment of surface roughness scattering capable of capturing such transport variation. The scattering is included directly through the real space propagation of carriers in the fluctuating potential associated with a randomly generated interface. We apply this approach to simulate inversion layer mobility in order to validate the model before its possible application in device variability simulations. Qualitative agreement is found with universal mobility data and avenues for possible calibration of surface and simulation parameters are highlighted.

Intrinsic parameter fluctuations in conventional MOSFETs until the end of the ITRS: A statistical simulation study

Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of intrinsic parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.

An improved description of the dielectric breakdown in oxides based on a generalized Weibull distribution

In this work, we address modal parameter fluctuations in statistical distributions describing charge-to-breakdown ( Q BD ) and/or time-to-breakdown ( t BD ) during the dielectric breakdown regime of ultra-thin oxides, which are of high interest for the advancement of electronic technology. We reobtain a generalized Weibull distribution ( q-Weibull), which properly describes ( t BD ) data when oxide thickness fluctuations are present, in order to improve reliability assessment of ultra-thin oxides by time-to-breakdown ( t BD ) extrapolation and area scaling. The incorporation of fluctuations allows a physical interpretation of the q-Weibull distribution in connection with the Tsallis statistics. In support to our results, we analyze t BD data of SiO 2 -based MOS devices obtained experimentally and theoretically through a percolation model, demonstrating an advantageous description of the dielectric breakdown by the q-Weibull distribution.

Analysis of fluctuations in semiconductor devices through self-consistent Poisson-Schrödinger computations

The effects of random doping and random oxide thickness fluctuations in metal-oxide-semiconductor field-effect transistors are analyzed by using self-consistent Poisson-Schrödinger computations. The Poisson and Schrödinger equations are solved by using the Newton iteration technique in which the Jacobian matrix is computed through first-order perturbation theory in quantum mechanics. A very fast technique based on linearization of the transport equations is presented for the computation of threshold voltage fluctuations. This technique is computationally much more efficient than the traditional Monte Carlo approach and it yields information on the sensitivity of threshold voltage fluctuations to the locations of doping and oxide thickness fluctuations. Hence, it can be used in the design of fluctuation resistant structures of semiconductor devices. Sample simulation results obtained by using this linearization technique are reported and compared with those obtained by using the Monte Carlo technique.

Quantum Corrections to the ‘Atomistic’ MOSFET Simulations

We have introduced in a simple and efficient manner quantum mechanical corrections in our 3D ’atomistic’ MOSFET simulator using the density gradient formalism. We have studied in comparison with classical simulations the effect of the quantum mechanical corrections on the simulation of random dopant induced threshold voltage fluctuations, the effect of the single charge trapping on interface states and the effect of the oxide thickness fluctuations in decanano MOSFETs with ultrathin gate oxides. The introduction of quantum corrections enhances the threshold voltage fluctuations but does not affect significantly the amplitude of the random telegraph noise associated with single carrier trapping. The importance of the quantum corrections for proper simulation of oxide thickness fluctuation effects has also been demonstrated.

Oxide thickness variation induced threshold voltage fluctuations in decanano MOSFETs: a 3D density gradient simulation study

We use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs in a statistical manner. A description of the reconstruction procedure for the random 2D surfaces representing the ‘atomistic’ Si–SiO2interface variations is presented. The procedure is based on power spectrum synthesis in the Fourier domain and can include either Gaussian or exponential spectra. The simulations show that threshold voltage variations induced by oxide thickness fluctuation become significant when the gate length of the devices become comparable to the correlation length of the fluctuations. The extent of quantum corrections in the simulations with respect to the classical case and the dependence of threshold variations on the oxide thickness are examined.

A direct tunneling memory using ultra-thin oxide and deca-nano floating gate structure

Direct tunneling memory (DTM) with nano-scale gate oxide accomplished low-voltage operation and full compatible process with MOSFET. DTM has a leakage stop barrier and sidewall control gate (CG) which prevent the overlap between a floating gate (FG) and source/drain (SD) extensions. In this work, improved DTM structure overcomes the first demonstration. To design DTM, we also developed a new simulator which considers direct tunneling phenomena and quantum effect at the oxide interface. The simulation shows that DTM has sufficient tolerance against oxide thickness (Tox) fluctuations.

Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs

This theoretical work investigates some aspects of direct tunneling gate current in ultra-thin gate MOSFET, as influence of bias, oxide thickness, and oxide thickness fluctuations. We study two alternative device architectures to reduce this effect. They consist in either increasing the insulator thickness using a high permittivity nitride/oxide stack or burying the channel, due to a tensile strained IV–IV heterostructure. The presented calculations have been performed by coupling a semi-classical approach of direct tunneling computation with the 2D Monte Carlo device simulation.

Analysis of electron energy distribution function in ultra-thin gate oxide n-MOSFETs using Monte Carlo simulation for direct tunneling gate current calculation

Direct tunneling (DT) current through ultra-thin gate oxide of a sub-0.1 μm MOSFET is calculated using the semi-classical approximation. The procedure consists in coupling the current calculation to 2D device simulation, whose role is to deliver the physical microscopic data necessary to the DT current estimation, i.e., the electron energy distribution at the interfaces and the potential barrier to be tunneled along the gate. We study the influence of drain voltage on gate current by assuming first a uniform gate oxide layer. It is shown that the contribution of hot carriers is very small and that the maximum of gate current density is located near the source. Then the oxide thickness fluctuations are taken into account. It is shown that high current densities run through the oxide layer in the vicinity of weak points, which is certainly related to the soft breakdown of the ultra-thin oxide layer. A correct agreement is achieved with experimental results.

Study of direct tunneling through ultrathin gate oxide of field effect transistors using Monte Carlo simulation

Direct tunneling gate currents of ultrathin gate oxide thickness metal oxide semiconductor field effect transistors (MOSFETs) are modeled in a two-step calculation procedure based on the treatment of physical microscopic data acquired during Monte Carlo device simulation. Gate currents are obtained by weighting the carrier perpendicular energy distribution at the Si/SiO2 and N+-poly–Si/SiO2 interfaces by the electron transmission probability, which is calculated by the one-dimensional Schrödinger equation resolution with the transfer-matrix method. The procedure is applied to a 0.07 μm gate length and 1.5 nm gate oxide thickness transistor, for which the gate and drain voltage influences on gate currents are studied by assuming at first a uniform gate oxide layer. It is shown that the maximum gate current is obtained for one of the two static points of complementary metal oxide semiconductor inverters: VGS=VDD and VDS=0, which raises a severe problem of standby power consumption. The contribution of hot carriers to the tunnel current is evaluated and is found to be small in case of such ultrathin oxide n-MOSFETs: contrary to thick (>5 nm) gate oxide transistors, the maximum gate current is not linked to the carrier energy peak in the channel but is located near the source well where the electron concentration is the largest. Oxide thickness fluctuations are then considered by meshing the oxide surface area and assuming a Gaussian law for the local oxide thickness deviation to the mean value. It is shown that a correct agreement is achieved with experimental published data when the oxide film nonuniformity is included in the calculation. Gate currents mapping for different bias conditions are given and analyzed, which show that very high current densities run through the oxide layer in the vicinity of weak points. An estimate of the surface through which flows the major part of the current is made, and a link between the highly nonuniform current leakage and the soft-breakdown mechanism of the oxide layer is proposed.

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10/sup 5/ times reliability improvement and a 0.3 approximately 1.8-V larger word-line voltage margin to write ONE data into the cell.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>