Oxide Semiconductor Field Effect Transistor Research Articles

High-Performance Sub-10 nm Two-Dimensional SbSeBr Transistors through Transport Orientation.

Exploring two-dimensional (2D) materials with a small carrier effective mass and suitable band gap is crucial for the design of metal oxide semiconductor field effect transistors (MOSFETs). Here, the quantum transport properties of stable 2D SbSeBr are simulated on the basis of first-principles calculations. Monolayer SbSeBr proves to be a competitive channel material, offering a suitable band gap of 1.18 eV and a small electron effective mass (me*) of 0.22m0. The 2D SbSeBr field effect transistor (FET) with 8 nm channel length exhibits a high on-state current of 1869 μA/μm, low power consumption of 0.080 fJ/μm, and small delay time of 0.062 ps, which can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices. Moreover, despite the monolayer SbSeBr having an isotropic me*, the asymmetrical band trends enable SbSeBr FETs to display transport orientation, which emphasizes the importance of band trends and provides valuable insights for selecting channel materials.

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

In this paper, a novel double-gate trench silicon-on-insulator lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (R on,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS, when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the R on,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/R on,sp) is increased by 397.2% from 3.6 MW cm−2 to 17.9 MW cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

The heat dissipation by the multi-needle electrode structure ionic wind generator

Ionic wind generated by atmospheric pressure discharge can be used for propulsion, heat dissipation, food drying, which shows the unique advantages of no mechanical parts and fast response. However, the wind speed and the energy efficiency of ionic wind generator are very low, which limit its application. In this paper, an ionic wind generator, constructed with needle-net electrode structure and powered by high-voltage positive dielectric current (DC) power supply, is built for cooling of a metal oxide semiconductor field effect transistor (MOSFET). The energy efficiency and wind speed of the ionic wind generator are optimized by adjusting the electrode structure and applied voltage amplitude. The results show that when the discharge spacing is fixed at 10 mm and the optimal needle spacing is 17.5 mm with 6 needles at 14 kV, the ionic wind velocity can reach a maximum value 3.20 m s−1 and the energy efficiency is 1.90%. Under optimal experimental conditions, the heat dissipation performance of MOSFET is significantly enhanced compared to using only a heat sink. With cooling by the ionic wind generator, the MOSFET junction temperature can be lowered by about 29 °C after 240 s operation.

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10−6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10−4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Fast and flexible solid-state linear transformer driver for plasma discharge based on metal oxide semiconductor field effect transistor.

A pulsed power supply with a short rise time and high repetition frequency is favorable to driving diffusive plasma for strongly oxidizing radical (O3, OH) generation and increasing the system's energy efficiency. In this paper, a 10-stage solid-state linear transformer driver (LTD) with a nanosecond rise time is developed to drive plasma for wastewater treatment. To decrease the rise time, a control system with low jitter is developed to improve the synchronization of pulses using an optocoupler isolation chip. A 10-stage LTD with a rise time of 6.2ns is realized in the case that the rise time of the single-stage LTD is 5.4ns. The results show that the LTD can generate pulses on a 300Ω resistive load with a repetition frequency of 10kHz, an amplitude of 8.80kV, an overshoot less than 3.97%, and a reverse overshoot less than 4.82%. The rise time (6.2-33.0ns), the pulse width (35.9-200.0ns), and the fall time (10.5-27.6ns) can be adjusted flexibly and independently by controlling the drive signals of metal oxide semiconductor field effect transistors. The pulsed generator is utilized to drive plasma in the needle-water electrode system. The preliminary experimental results show that the plasma includes abundant oxygen atoms and hydroxyl radicals with high activity, and it is suitable for wastewater treatment.

Transient turn-on characteristics of Si RBDT and SiC MOSFET under nanosecond current pulse range

With the development of pulse power supplies, solid-state semiconductor switches are required to have fast switching speeds and low losses. Both Reverse blocking diode thyristor (RBDT) and silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) have fast turn-on speed, making them suitable candidates for short pulse generator. In this paper, the transient turn-on characteristics of Si RBDT and SiC MOSFET are analyzed theoretically and validated experimentally. Si RBDT and commercial 1.2 kV/81A SiC MOSFET are comparatively investigated in switching current pulse with a rise time of several hundreds of nanoseconds. (1) The anode current of RBDT could rise exponentially because of the latch-up effect of Si RBDT, while the drain current of SiC MOSFET tends to be saturated. (2) Utilizing the current rise time (Trise) to represent the switching speed, SiC MOSFET can switch faster when the current is lower than 400A. With the increase of the current, Si RBDT presents faster turn-on speed and lower switching loss due to the regenerative action of the two coupled transistors. (3) The transient characteristics of Si RBDT include a voltage-controlled inductance, while SiC MOSFET contains a current-controlled inductance based on the current rise time, respectively. With the increasing of the main voltage, the equivalent inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. For SiC MOSFET, the equivalent inductance increases until the drain current remains stable for a given gate voltage. This paper confirms the advantages of Si RBDT and SiC MOSFET in different situations.

Blocker tolerant cascode LNA for Wifi & IoT applications

SummaryWithin the domain of contemporary wireless communication systems, crafting Low‐Noise Amplifiers (LNA) holds a pivotal significance in achieving heightened signal sensitivity and comprehensive system efficacy and suppresses noise contributions from subsequent stages. Additionally, the low noise figure (NF) and high gain are critical LNA performance parameters in portable applications. Normally, LNA contains issues in noise performance, amplification, bandwidth, gain, and stability. To overcome these challenges, there must be a proper selection of transistors, harmonious impedance calibration, bias optimization, and circuit fine‐tuning. Moreover, metal oxide semiconductor field effect transistors (MOSFETs) are a popular choice in LNA design because of their excellent noise performance, high input impedance, complementary metal‐oxide semiconductor (CMOS) integration capabilities, low power operation, and suitability for a wide range of frequency applications. Through simulation and iterative enhancement, the LNA showcases remarkable Noise Figure, amplification, and linearity over a designated frequency span. This creation contributes to the advancement of radio frequency (RF) circuitry by designing an approach for LNA crafting that harmonizes conflicting prerequisites and unveils effective noise mitigation tactics. The outcomes emphasize the importance of a deliberated circuit architecture and parameter adjustment in accomplishing superlative LNA capabilities, rendering it fit for assimilation into diverse communication systems that demand minimal noise and heightened sensitivity.

Calculating and analyzing time delay in zigzag graphene nanoscrolls based complementary metal-oxide-semiconductors

Graphene Nano Scrolls (GNSs) and Zigzag graphene nanoscrolls (ZGNSs) are semi-one-dimensional materials with exceptional electrical and optical properties, making them attractive to be used in nanoelectronics and complementary metal–oxide–semiconductor (CMOS) technology. With in CMOS device technology, time delay is a crucial issue in the design and implementation of CMOS based ZGNSs. Current paper focus is on ZGNSs application in the channel area of metal–oxide–semiconductor field-effect transistors (MOSFETs) in CMOS technology. We studied analytically, the importance of different parameters on time delay reduction, resulting in faster switching and higher frequency in integrated circuits (ICs). The results of this research demonstrates that, the ZGNS-based CMOS proves considerable variations in the current due to the geometrical parameters, such as chirality number, channel length, and nanoscroll length which can be engineered to produce faster ICs.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Tunneling field-effect transistors with two-dimensional BiN as the channel semiconductor

The lack of suitable channel semiconductor materials has been a limiting factor in the development of tunneling field-effect transistor (TFET) architectures due to the stringent criteria of both air stability and excellent gate-tunable electronic properties. Here, we report the performance limits of sub-10-nm double-gated monolayer (ML) BiN TFETs by utilizing first-principles quantum-transport simulations. We find that ML BiN possesses an indirect bandgap of 0.8 eV and effective masses of 0.24m0 and 2.24m0 for electrons and holes, respectively. The n-type BiN TFETs exhibit better performance than the p-type ones, and the on-state current can well satisfy the requirements of the International Roadmap for Devices and Systems for both high-performance and low-power standards. Notably, we find that the BiN TFETs exhibit distinguished gate controllability with an ultra-low subthreshold swing below 60 mV/decade even with a small gate length of 6 nm, which is superior to the existing field-effect transistors, such as black phosphorus TFETs, GeSe TFETs, and BiN metal–oxide–semiconductor field-effect transistors. Furthermore, the BiN TFETs are endowed with the potential to realize high switching speed and low-power consumption applications because of their extremely short delay time and ultra-low power-delay product. Our results reveal that the ML BiN is a highly competitive channel material for the next-generation TFETs.

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs due to Power Cycling Tests

Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg >> Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Performance Improvement of a ZnGa2O4 Extended-Gate Field-Effect Transistor pH Sensor.

ZnGa2O4 sensing films were prepared using an RF magnetron sputtering system and connected to a commercial metal oxide semiconductor field-effect transistor (MOSFET) as the extended-gate field-effect transistor (EGFET) to detect pH values. Experimental parameters were adjusted by varying the oxygen flow rate in the process chamber to produce ZnGa2O4 sensing films with different oxygen ratios. These films were then treated in a furnace tube at an annealing temperature of 700 °C. The sensitivity and linearity of the constant current mode and the constant voltage mode were measured and analyzed in the pH range of 2-12. Under the deposition conditions with an oxygen ratio of 6%, the sensitivity reached 23.14 mV/pH and 33.49 μA/pH, with corresponding linearity values of 92.1 and 96.15%, respectively. Finally, the sensing performance of the ZnGa2O4 EGFET pH sensor with and without annealing processes was analyzed and compared.

Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs

We investigated the effects of the column length and fabrication method of the superjunction (SJ) structure on the reverse recovery characteristics of 1.2 kV silicon carbide (SiC) SJ metal–oxide–semiconductor field-effect transistors (MOSFETs). The voltage slope (dV/dt) and reverse recovery current slope (dir/dt) values during the reverse recovery of the SJ-MOSFETs with the SJ structure formed by Aluminum (Al) ion implantation were comparable to the values of MOSFETs without SJ structure at room temperature (RT), but they increased markedly with temperature. This is caused by the reduced p-column carrier concentration at RT during short recovery transient time due to the deep hole trap (DI center) introduced by ion implantation. At 175 °C, a softer reverse recovery waveform was obtained by shortening the SJ columns. Besides, Al ion implanted SJ-MOSFETs exhibited a weaker current dependence of the reverse recovery charge Qrr at 175 °C indicating a lower carrier injection level compared to the SJ-MOSFETs with the SJ structure formed by trench formation and epitaxial growth. This is caused by the short carrier lifetime of the SJ columns due to the Al ion implantation defects. The short and Al ion implanted SJ columns are effective for soft reverse recovery characteristics in SiC-SJ-MOSFETs.

Revolutionizing Technology with Spintronics: Devices and Their Transformative Applications

The scaling of metal oxide semiconductor field effect transistors (MOSFETs) for data storing and logic circuit operation has reached a critical point, beyond which further scaling poses various secondary issues. These problems include short channel effects, hot carrier effects (HCEs), and reliability concerns. However, a promising alternative called spintronics has recently emerged as a highly exciting technology. Spintronics considers both the charge and spin of electrons in device operations and offers superior properties compared to MOSFETs.Researchers have reported numerous spintronics devices that exhibit significant potential in memory and logic circuits when integrated with complementary metal oxide semiconductor (CMOS) technology. These devices not only possess excellent scalability but also consume less power than MOSFETs at the nano-scale level. This article aims to provide a comprehensive review of the current state, future prospects, and challenges associated with spintronics devices.

Research and analysis of electromagnetic interference of a motor drive control system based on PMSM with SiC MOSFET for new energy electric vehicles

Sustainable development in the 21st century faces significant challenges due to finite reserves of fossil fuels and environmental pollution. In the context of new energy electric vehicles (NEEVs), the wide-bandgap semiconductor known as the silicon carbide–metal oxide–semiconductor field-effect transistor (SiC MOSFET) and the permanent magnet synchronous motor (PMSM) have emerged as advantageous sources. However, the use of these components gives rise to electromagnetic interference (EMI) issues, which impede the achievement of electromagnetic compatibility (EMC) standards in the motor drive control system. This paper aims to elucidate the generation mechanism, propagation path, and test infrastructure of EMI. Furthermore, it proposes a system-level conducted EMI equivalent circuit model for the motor drive control system, encompassing the power battery pack, busbar cable, LISN, three-phase inverter, and PMSM. Building upon this foundation, the principles for suppressing and optimizing EMI noise are discussed. The paper concludes with the validation of simulations and experimental results, which demonstrate the effectiveness of the proposed approach. It is anticipated that professionals with an interest in the field of EMI/EMC will find this paper to be of both theoretical and practical importance.