Oxide Semiconductor Field-effect Transistor Devices Research Articles

Observation of MOSFET-like behavior of a TFT based on amorphous oxide semiconductor channel layer with suitable integration of atomic layered deposited high-k gate dielectrics

A series of different high κ dielectrics such as HfO2, ZrO2, and Al2O3 thin films were studied as an alternative material for the possible replacement of traditional SiO2. These large areas, as well as conformal dielectrics thin films, were grown by the atomic layer deposition technique on a p-type silicon substrate at two different deposition temperatures (150 and 250 °C). Atomic force microscopic study reveals that the surface of the films is very smooth with a measured rms surface roughness value of less than 0.4 nm in some films. After the deposition of the high κ layer, a top metal electrode was deposited onto it to fabricate metal oxide semiconductor capacitor (MOSCAP) structures. The I–V curve reveals that the sample growth at high temperatures exhibits a high resistance value and lower leakage current densities. Frequency-dependent (100 kHz to 1 MHz) C–V characteristics of the MOSCAPs were studied steadily. Furthermore, we have prepared a metal oxide semiconductor field-effect transistor device with Al-doped ZnO as a channel material, and the electrical characteristic of the device was studied. The effect of growth temperature on the structure, surface morphology, crystallinity, capacitance, and dielectric properties of the high κ dielectrics was thoroughly analyzed through several measurement techniques, such as XRD, atomic force microscopy, semiconductor parameter analysis, and ultraviolet-visible spectroscopy.

Quantum physics applied to modern optical metal oxide semiconductor transistor

In recent years, traditional complementary metal–oxide–semiconductor (CMOS) scaling techniques have begun to reach the technological limits of available materials. A revolution in block-to-block communication is necessary to meet the ever-growing demand for microprocessor computational power. On-chip optical communication has been designated as a promising solution to circumvent the CMOS scaling bottlenecks: second-order phenomenon, which causes significant interconnect delays, and the nonscalability of the thermal voltage, which becomes significant in submicron CMOS technology. The metal oxide semiconductor quantum well transistor, a silicon-on-insulator metal–oxide–semiconductor field-effect transistor device, with a channel thickness reduced to the single nanometer scale is examined. The nanometric gate oxide, silicon, and buried oxide heterostructure in the channel forms a quantum potential well, creating discrete sub-bands within the silicon layer. Inter-sub-band-transitions within the quantum well may allow for radiative recombination in indirect band gap materials.

Growth of aluminum oxide on silicon carbide with an atomically sharp interface

The development of SiC wafers with properties suitable for electronic device fabrication is now well established commercially. A critical issue for developing metal–oxide–semiconductor field effect transistor devices of SiC is the choice of dielectric materials for surface passivation and insulating coatings. Although SiO2 grown thermally on SiC is a possibility for the gate dielectric, this system has a number of problems related to the higher band gap of SiC, which energetically favors more interface states than for SiO2 on Si, and the low dielectric constant of SiO2 leading to 2.5× higher electric fields across the oxide than in the surface of SiC, and to a premature breakdown at the higher fields and higher temperatures that SiC devices are designed to operate under. As a replacement for SiO2, amorphous Al2O3 thin film coatings have some strong advocates, both for n- and p-type SiC, due to the value of its band gap and the position of its band edges with respect to the band edges of the underlying sem...

Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

Crystal thickness and extinction distance measurements by convergent beam electron diffraction fitting and application in quantitative TEM holography analysis on p-n junctions

A modified model function is proposed to determine Si crystal thickness and extinction distance by fitting of the convergent-beam electron diffraction (CBED) intensity based on the dynamical diffraction and absorption theories. The previous fitting method employs two separate functions to simulate the elastic and inelastic parts of CBED intensity, while the present work uses a single model for the simulation. At an electron beam energy of 300 kV, the model demonstrates very fast and accurate thickness measurements ranging from 58 to 334 nm for the Si crystal. The minimum measurable thickness is around three times smaller compared with the conventional K–A plot method. From the fitting, the extinction distance of the Si (004) diffraction was determined to be 183.03 ± 2 nm, which is useful for the determination of the Si crystal structure factor. In conjunction with the transmission electron microscope holography technique, the authors study the electrostatic built-in potential across the p-n junction of the source and drain of a metal–oxide–semiconductor field effect transistor device.

Investigation of atomic layer deposited beryllium oxide material properties for high-k dielectric applications

Beryllium oxide (BeO) is a wide band gap alkaline earth oxide material that has recently shown significant promise as a high-k dielectric material in Si and III-V metal–oxide–semiconductor field effect transistor devices. However, many of the basic material properties for BeO thin films utilized in these devices have not been reported or remain in question. In this regard, the authors report an investigation of the chemical, physical, electrical, and mechanical properties of BeO thin films formed via atomic layer deposition (ALD). Combined Rutherford backscattering and nuclear reaction analysis measurements show that ALD BeO thin films exhibit a low hydrogen content (<5%) and are nearly stoichiometric (Be/O ≅ 1.1 ± 0.05). Reflection electron energy loss spectroscopy measurements reveal a wide band gap of 8.0 ± 0.14 eV, and nanoindentation measurements show that ALD BeO has a high Young's modulus and hardness of 330 ± 30 and 33 ± 5 GPa, respectively.

Influence of Al/TiN/SiO2 structure on MOS capacitor, Schottky diode, and fin field effect transistors devices

Titanium nitride (TiN) films were tested for their suitability as upper electrodes in metal–oxide–semiconductor (MOS) capacitors and Schottky diodes and as metal gate electrodes in fin field effect transistor devices. TiOxNy formation on TiN surfaces was confirmed by x-ray photoelectron spectroscopy and appears to be associated with exposure of the metal electrodes to ambient air. In order to avoid the formation of TiOxNy and TiO2, a layer of aluminum (Al) was deposited in situ after the TiN deposition. TiN work function was calculated for the devices to study how dipole variation at the interface TiN/SiO2 influences TiN work function. TiOxNy and TiO2 formation at the film surface was found to affect the dipole variations at the TiN/SiO2 interface increasing the dipole influence on MOS structure. Furthermore, the estimated values TiN work function are suitable for complementary metal–oxide–semiconductor (CMOS) technology. Finally, this work had shown that Al/TiN structure can be used in CMOS technology, especially on n-type metal–oxide–semiconductor field effect transistor devices.

Evaluation of Interface Property and DC Characteristics Enhancement in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Stress Memorization Technique

In this letter, the advanced 40 nm technology n-channel metal–oxide–semiconductor field-effect transistor devices using the stress memorization technique (SMT) are presented. We demonstrate that SMT process would not affect the electrical characteristics of devices and can introduce higher tensile stress on channels, which enhances drive current. Through charge pumping measurement, it can be verified that SMT does not affect Si/SiO2 interface quality. Moreover, SMT-induced higher tensile stress decreases not only scattering coefficient but also tunneling attenuation length, resulting in smaller input-referred noise, which represents an intrinsic advantage of low-frequency noise performance.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.

Confining P diffusion in Si by an As-doped barrier layer

The miniaturization of Si-based devices requires control of doping profile, which makes the understanding of dopant interaction and diffusion in Si critical. The authors have studied the effect of As doping on P diffusion in Si using first-principles calculations. The authors found a form of As-vacancy complex is energetically favorable, allowing As to consume the vacancy so as to prohibit the vacancy-mediated P diffusion. Also, in the vicinity of As, the vacancy-mediated P diffusion barrier is increased, decreasing further the P mobility. The results provide useful guidance for designing As-doped barriers to block P diffusion in Si wafer processing and metal oxide semiconductor field-effect transistor device fabrication.

Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 µm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 µm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 µm showed the longest on-resistance hot-carrier lifetime of 9.34 ×105 s, along with a breakdown voltage of 22 V and an on-resistance of 23 mΩ·mm2.

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

We investigate the effects of silicon cap layer thinning on channel carrier confinement in silicon/strained silicon-germanium (Si/SiGe) metal–oxide–semiconductor (MOS) structures. The silicon cap thickness is shown to have a critical influence on the induced parasitic channel in the silicon cap, which lowers the transconductance value of the buried SiGe channel in hole carrier channel p metal–oxide–semiconductor field-effect transistor devices. This can have serious consequences on future implementation of SiGe ultrashort channel devices where gate induced parasitic channel and short channel effects can be pronounced. An exact methodology is devised for consumption of silicon cap layer using a modified Radio Corporation of America surface standard clean self-terminating chemical oxide and rapid thermal oxide growth. This provides (i) precise control over the silicon cap and thermal oxide thickness and (ii) a limit on the amount of thermal budget induced strain relaxation in the buried SiGe layer. The threshold voltages for inversion of carriers at the SiO2/Si and the Si/SiGe interfaces are extracted as functions of Si cap thickness. A transition from dual to single channel operation in MOS devices at room temperature on thinning the silicon cap layer is observed with capacitance–voltage measurements. Cross-section transmission electron microscopy and secondary ion mass spectroscopy techniques are used to calibrate and support the developed methodology for Si cap layer etch control and the effect of Ge species at the oxide–heterostructure interface. There is a high fixed charge density, which indicates Ge pileup at the SiO2/SiGe interface. Our analysis suggests that about 1 nm of silicon cap retention is necessary to minimize the gate induced parasitic channel and to decouple the oxide interface trap influence on the channel carriers in the SiGe.

Diamond field-emission triode with low gate turn-on voltage and high gain

A diamond field-emission triode with low gate turn-on voltage of 10 V and high gain factor of 250 is reported. The gated diamond triode was fabricated with a self-aligning gate technique from a silicon-on-insulator wafer. Ia–Vg plot of emission characteristics from four tips shows a very low gate turn-on voltage of 10 V and high emission current of 4 μA at gate voltage of 20 V. Ia–Va plots of emission characteristics demonstrate the desired saturation behavior of field-emission transistor with a high voltage gain of 250. The low turn-on gate voltage and high gain factor are comparable to solid-state metal–oxide–semiconductor field-effect transistor devices, confirming the diamond field-emission triode has significant potential for integrated circuit-compatible vacuum microelectronic applications.

Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal–oxide–semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy

We have directly measured nanoscale electronic features associated with a 120 nm physical gate length p-channel silicon metal–oxide–semiconductor field-effect transistor device structure including n+ superhalo implants using cross-sectional scanning capacitance microscopy (SCM). A dc bias-dependent voltage series of SCM images representing nine bias conditions from 2 to −2 V in 0.5 V steps was obtained. The SCM contrast observed varies with the ac and dc bias applied to the sample and allows delineation of the device features, including the p+ source and drain contacts, p+ source and drain extensions, p+ polycrystalline silicon gate, electrical p–n junction, n-well, and n+ superhalo implants. It is demonstrated that the superhalo implant features are imaged only under specific SCM bias conditions. Detailed analysis of the resulting SCM contrast indicates an apparent channel length of 73±11 nm, and reveals clear asymmetry in the individual lobes of the n+ superhalo implant features.

Thermal reaction of nickel and Si0.75Ge0.25 alloy

The interfacial reactions and chemical phase formation between nickel and ultrahigh vacuum chemical vapor deposited Si0.75Ge0.25 alloy have been studied within the temperature range of 300–900 °C for forming low resistive and uniform silicide films for future application in SiGe based metal–oxide–semiconductor field effect transistor devices. The silicided films were characterized by the x-ray diffraction, Auger electron spectroscopy, scanning electron microscopy, transmission electron microscopy, and micro-Raman microscopy techniques. Smooth and uniform nickel monogermanosilicide NiSi0.75Ge0.25 films have been observed for samples annealed at around 400–500 °C. For annealing temperatures of 500 °C and above, Ge-rich Si1−zGez grains where z>0.25 were found among Ge deficient Niy(SiwGe1−w)1−y grains where w<0.25 and the Niy(Si1−wGew)1−y phase is thermally stable up to an annealing temperature of 800 °C. We found that the Ni/SiGe reaction is mainly diffusion controlled with Ge and Ni as the dominant diffusing species compared to Si during the annealing process. In addition, Ge has been found to promote agglomeration especially above 700 °C, leading to an abrupt increase in the sheet resistance.

Incorporation of helium-implant-induced cavities near the active regions of metal–oxide–semiconductor devices: Effects on dc electrical characteristics

Cavities, formed by helium implantation and subsequent annealing, have proved to be effective at trapping metal impurities within silicon. This has led to interest in their use as proximity gettering sites. In this investigation, cavity populations were formed by helium implants of energy 40 keV and dose 5×1016 cm−2 followed by annealing at 900 °C. This regime produces cavities with a mean void radius of 20 nm, located between 100 and 350 nm below the silicon surface. The effect of the presence of such cavities near the active areas of 1.2 μm p-type metal–oxide–semiconductor field-effect transistor devices is described. Electrical characterization of wafers, which have been implanted with helium on the front or rear silicon surface, has been carried out to determine whether the inclusion of void populations near the active regions of silicon devices is detrimental. These measurements found no evidence of any detrimental effect on the performance of working devices.

Scaling considerations for high performance 25 nm metal–oxide–semiconductor field effect transistors

This article presents a systematic simulation-based study on scaling gate oxide thickness and the source–drain extension junction depth to achieve high performance 25 nm metal–oxide–semiconductor field effect transistor devices for low power operation. In order to obtain the target 25 nm devices, complementary metal–oxide–semiconductor (CMOS) technologies were designed by scaling source–drain extension junction depths to 14, 20, and 26 nm and the corresponding gate lengths to 40, 50, and 60 nm, respectively. Each technology was separately optimized for each value of the equivalent gate oxide thickness 1, 1.5, and 2 nm to achieve the target value of off-state leakage current of about 10 nA/μm for 25 nm devices. The simulation results show that for a low voltage operation of 25 nm devices with a fixed off-state leakage current, the magnitude of threshold voltage, subthreshold slope, and the drain-induced barrier lowering is too high while the magnitude of drive current is too low for gate oxide thickness ⩾1.5 nm. However, the variation in the magnitude of threshold voltage, subthreshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of source–drain extension junction depth between 14 and 26 nm. It is also found that the increase in the gate delay is ⩾12% for 25 nm devices with the source–drain extension junction depth ⩾20 nm compared to the similar devices with a source–drain extension junction depth of about 14 nm. This article demonstrates that the continuous scaling of gate oxide thickness below 1.5 nm and the source–drain extension junction depth below 20 nm is essential for achieving high performance CMOS technologies with 25 nm nominal devices for low power application.

Two-dimensional dopant profile of 0.2 μm metal–oxide–semiconductor field effect transistors

In this article, we report our progress in two-dimensional (2D) dopant profiling of metal–oxide–semiconductor field effect transistor devices fabricated with 0.2 μm technology by using dopant selective etching followed with atomic force microscope imaging (DSE/AFM). By comparing device simulation results based on our measurement with electrical measurement results, we have found that in these small devices the depletion region can have a significant effect on the results of dopant concentration conversions from the selective etching data, and the necessary correction can be found by a proper estimation of the depletion width. Here we discuss the factors that affect the etching reproducibility and reliability and show our approaches to these challenges. Our results show that DSE/AFM is a useful technique for 2D dopant profiling with certain advantages if it is dealt with properly.

Ultrathin silicon oxynitride film formation by plasma immersion nitrogen implantation

A method is proposed to prepare ultrathin silicon oxynitride films for gate dielectrics used in deep submicron metal–oxide–semiconductor field effect transistor device structures, namely plasma immersion N implantation into SiO2 films. Plasma immersion implantation pulse voltages in the range 200–1000 V, and fluences from 1016 to 1017 N cm−2 were implanted into thermally grown SiO2 films, with thicknesses between 3 and 6 nm. The areal densities of N and O in the resulting oxynitride films were determined by nuclear reaction analysis, before and after annealing in high-vacuum. N, O, and Si profiles in the films were determined with subnanometric depth resolution by medium energy ion scattering. The results indicate that plasma immersion ion implantation allows for shallow and controlled deposition of significant amounts of nitrogen (up to 3.8 nm of equivalent Si3N4 thickness). Implantation is accompanied by moderate damage at the oxynitride/Si interface which can be recovered by thermal annealing.

Metal Silicides: Active elements of ULSI contacts

As device dimensions scale to the 0.1 urn regime, the self-aligned suicide (SALICIDE) contact technology increasingly becomes an integral part of both the ultra-shallow junction and the metal oxide semiconductor field-effect transistor device itself. This paper will discuss the effect of suicide materials and formation processes on suicide stability, junction consumption, the ability to accurately profile shallow junctions, and contact resistance in series with the channel. The use of suicides as diffusion sources (SADS) provides an important pathway toward optimization of suicide technology. Diffusion of boron and arsenic from nearly epitaxial layers of CoSi2, formed from bilayers of Ti and Co, offer good suicide stability, ultra-shallow, low-leakage junctions, and low contact resistance.