Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

Abstract

In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 µm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 µm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 µm showed the longest on-resistance hot-carrier lifetime of 9.34 ×105 s, along with a breakdown voltage of 22 V and an on-resistance of 23 mΩ·mm2.