Sacrificial Oxide Layer Research Articles

An In-Plane High-Sensitivity, Low-Noise Micro-g Silicon Accelerometer With CMOS Readout Circuitry

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.

A surface micromachining process for the development of a medium-infrared tuneable Fabry–Perot interferometer

Electrostatically driven moving micromirrors are proposed in this work for the fabrication of a tuneable Fabry–Perot interferometer. The device is intended for a gas sensing application, and operates in the medium infrared spectral range. In order to achieve high filter selectivity and to reduce the loss of transmitted light it is of utmost importance that the mirrors are kept parallel after release and during device actuation. Surface micromachined polysilicon mirrors have been selected for this application. This technology provides an accurate control of the air gap between mirrors. The internal homogeneous stress and stress gradient states of the polysilicon films have a great influence on mirror deflection upon release. The micromachining process developed to obtain flat-surface micromirrors with an accurate air gap, by reducing the stress-induced polysilicon deflection and building thick oxide sacrificial layers is described in this work.

Removal of dry etch damage in p-type GaN by wet etching of sacrificial oxide layer

We describe etch-induced damage in p-type GaN caused by an inductively coupled Cl2/Ar/O2 plasma and a method for its removal by means of wet etching. When p-GaN was etched by a Cl2/Ar/O2 plasma, an oxide layer was formed on the p-GaN surface by the oxygen in the plasma. The electrical properties of the etched p-GaN films deteriorated, as a result of the oxide on the surface, as well as etch-induced damage. However, a HF postwet etching of the dry-etched samples effectively removed the sacrificial oxide layer on the surface that contained the etch-induced defects and damage, resulting in improved characteristics in surface morphology and photoluminescence in the etched p-type GaN.

Novel High-Q Suspended Inductors on Alumina Ceramic Substrates

ABSTRACTThe growth of the wireless industry over the past ten years has created a need for good quality passive components, and in particular high Q factor inductors. There has been a large amount of work aimed at improving the quality factors of inductors on both silicon and ceramic/insulating substrates. KAIST and other research groups have explored a MEMS technique, releasing the inductor coil to create an air gap between the coil and underpass, on silicon [1]. Typically the inductor coil has been separated by a 50 to 100μm air gap and has required special processing such as a dual exposure photoresist mold [1]. In the present work, suspended inductor coils have been fabricated and characterized on an alumina ceramic substrate [2]. The gap used was only 1μm and this was enough to increase the self-resonance frequency by up to 4GHz after release. The inductor coils were created in 6–10μm thick electroplated gold and the underpass in an aluminum layer. A sacrificial LPCVD oxide layer was used as the released dielectric. In the present study a range of inductance from 1 to 30nH was explored before and after release. The Q factors achieved in this work range from 40 to 70 in the 2 to 10 GHz range, which are some of the best Q factors reported for planar inductors (see Table I). In addition, since the architecture allowed the use of three metal layers, released transformers were also fabricated. They showed promising high frequency performance, which also will be presented. Minimum insertion loss better then –2dB was achieved between 10–12 GHz. The above described process is simple, precise, and manufacturable with the ability to extend the useful range of inductors to higher frequencies (1–10 GHz).

Electrical and Mechanical Properties of Micromachined Vacuum Cavities

This paper reports the measured electrical and mechanical properties of micromachined vacuum cavity resonators made on bonded silicon on insulator (SOI) wafers using the new plugup process. With this novel process it is possible to fabricate microelectromechanical devices without the attack of hydrofluoric acid against the aluminium metallisation during the sacrificial oxide layer etching. Another merit of the new process is its improved immunity to stiction.The moving parts of the microresonator are constructed of single crystal silicon with very low internal stress. In surface micromachining the structures are typically made of CVD polysilicon, which has higher internal stress. Thus the mechanical properties of these resonators on SOI are governed by the elastic rigidity of the material used and the geometry of the structure which is affected by both design parameters and process variations.The mechanical losses of the cavity structure are caused by the supports at edges of resonator and the acoustic damping. The pressure during LPCVD process used for sealing determines the pressure remaining in the cavity. With the plug-up process one can fabricate vacuum cavities on SOI substrates without deteriorating the silicon material properties or its surface quality. These cavities can be utilised for realization of a wide variety of single crystal micromechanical devices and in monolithical integration of SOI/MEMS and integrated circuits.

A hybrid Nb/CMOS integration process for superconducting tunnel junction imaging arrays

A process for hybrid superconductor/CMOS integration was developed for the fabrication of extremely sensitive color-imaging arrays using superconducting tunnel junctions. A Nb-AlO/sub x/-Nb process was used to fabricate arrays of junctions directly on top of CMOS devices. The CMOS wafers required the development of a planarization process suitable for subsequent tunnel-junction fabrication. The process involved the deposition of a sacrificial oxide layer by electron cyclotron resonance plasma-enhanced chemical vapor deposition, chemical-mechanical polishing, and a layer of spin-on glass. A process was also developed for via contacts through the oxide layer that optimized the stability of the contacts. The critical current spreads of the arrays (50 junctions) were as small (spread about 1% for 3 /spl mu/m /spl times/ 3 /spl mu/m junctions) as on bare silicon wafers.

The HARPSS process for fabrication of precision MEMS inertial sensors

The high aspect-ratio combined poly- and single-crystal silicon micromachining technology (HARPSS) and its application to fabrication of precision MEMS inertial sensors are presented. HARPSS is a single wafer, all silicon, front-side release process which is capable of producing 10–100's of microns thick, electrically isolated, 3-D poly- and single-crystalline silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns. High aspect-ratio (>50:1) polysilicon structures are created by refilling 100's of microns deep trenches with polysilicon deposited over a sacrificial oxide layer. This technology provides features required for precision micromachined inertial sensors. The all-silicon feature of this technology improves long term stability and temperature sensitivity while fabrication of large area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of magnitude.

Measurement of Oxide Etch Rate of SOI Structure using near IR Microscopy

The sacrificial oxide etching is one of the key steps in fabrication of micromechanical devices on bonded silicon on insulator (SOI) wafers. The determination of the etch rate of buried oxide layers in bonded SOI wafers from scanning electron microscopy (SEM) cross-sections is a rather tedious and time consuming task. However, the knowledge of the etch front propagation is essential for ensuring the success of etch release and thus the device operation. In this paper a fast and non-destructive method for measurement of sacrificial oxide layer etch rates is described. The pattern and time dependencies of SOI structure etching in concentrated hydrofluoric acid are studied by near infrared microscopy. The etch length of the SOI can be accurately measured with IR microscope. The measurement results were also verified by SEM cross-sections. The observed variation in etch rates can be explained by the SOI interface quality and not by any aspect ratio dependency caused by varying structure layer thickness. In the used etch times for etching of the thermal oxide the etch-rate seems to be limited by the bonded interface quality and not by transport limitations. The results of these experiments and some application examples are shown. Other possible applications, limitations and error sources of this method are discussed.

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.

Towards the improvement of the stability of a-Si:H pin devices

This paper deals with a new process to improve the stability of a-Si:H pin solar cells deposited in a single batch process by proper passivation of the interfaces. The process consists in removing partially a deposited sacrificial oxide layer grown between the p/i or i/n interfaces by SF 6 etching. This layer is an absorber of defects and impurities that are introduced in the interfaces, mainly from the chamber walls and the substrate surface. The results achieved in laboratory samples lead to devices in which the fill factor and short circuit current density were improved respectively towards 75% and 16.5 mA cm −2, with a final working efficiency of about 9.5%.

Integration of sputtered silicon microstructures with pre-fabricated CMOS circuitry

This paper describes a novel fabrication process for creating sputtered silicon microstructures similar to those commonly made using LPCVD polysilicon. Unlike LPCVD polysilicon processes, however, this low-temperature sputtered process is compatible with pre-fabricated aluminum-metallized CMOS circuitry. Both polyimide and conventional oxide sacrificial layers were used, with the former being removed using oxygen plasma. This dry-release step eliminated the need for critical point drying commonly required for wet releases. To evaluate sputtered silicon for use in MEMS, several properties were investigated, including in-plane stress, strain gradient, density, surface roughness, electrical resistivity, and HF permeability. Tensile stress values lower than 100 MPa were achieved by varying the deposition parameters. Average strain gradients were an inverse square function of thickness. Densities were slightly lower than bulk silicon values. Surface roughness was less than 6 nm rms. The electrical conductivity of the silicon bare films was low but was increased by cladding the sputtered silicon structural layers in symmetric, 50 nm thick layers of titanium–tungsten. Underlying CMOS transistors showed no more than a 3% increase in their maximum saturation current after mechanical layer processing. Finally, to demonstrate the technology, an electrostatically deflected plate structure was fabricated above a capacitance measurement circuit and performance results are presented.

High aspect-ratio combined poly and single-crystal silicon (HARPSS) MEMS technology

This paper presents a single-wafer high aspect-ratio micromachining technology capable of simultaneously producing tens to hundreds of micrometers thick electrically isolated poly and single-crystal silicon microstructures. High aspect-ratio polysilicon structures are created by refilling hundreds of micrometers deep trenches with polysilicon deposited over a sacrificial oxide layer. Thick single-crystal silicon structures are released from the substrate through the front side of the wafer by means of a combined directional and isotropic silicon dry etch and are protected on the sides by refilled trenches. This process is capable of producing electrically isolated polysilicon and silicon electrodes as tall as the main body structure with various size capacitive air gaps ranging from submicrometer to tens of micrometers. Using bent-beam strain sensors, residual stress in 80-/spl mu/m-thick 4-/spl mu/m-wide trench-refilled vertical polysilicon beams fabricated in this technology has been measured to be virtually zero. 300-/spl mu/m-long 80-/spl mu/m-thick polysilicon clamped-clamped beam micromechanical resonators have shown quality factors as high as 85 000 in vacuum. The all-silicon feature of this technology improves long-term stability and temperature sensitivity, while fabrication of large-area vertical pickoff electrodes with submicrometer gap spacing will increase the sensitivity of micro-electromechanical devices by orders of magnitude.

A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical–mechanical planarization

A multilayer thin film structure (SiO 2/SiN x /SiO 2) with a one-step chemical–mechanical polish (CMP) process is developed for shallow trench filling and planarization for ULSI devices in the quarter micron regime. By fine-tuning the plasma-enhanced chemical vapor deposition (PECVD) conditions we successfully modified the stoichiometry and other characteristics of the as-deposited SiN x and oxide films. As these film characteristics are changed, the CMP removal rate selectivity between sacrificial oxide and nitride stopper layer can also be adjusted. Correspondingly, the CMP process latitude for shallow trench isolation in 0.25 μm memory devices can be broadened by sequentially depositing multilayered oxide and nitride films with adjustable characteristics and CMP removal rates. Dishing-free wide trench areas with excellent planarity can be achieved through the integration of the proposed multilayered PECVD oxide/nitride scheme and the one-step CMP process.

Fabrication and characterization of surface micromachined capacitive ultrasonic immersion transducers

In this paper, several innovative steps used in fabricating surface micromachined capacitive ultrasonic immersion transducers are reported. The investigation is focused on major steps in the device fabrication processes necessary to optimize transducer performance. Such steps include membrane formation, vacuum sealing, and electrode metallization. Three transducer membrane structures are evaluated: a nitride membrane with an oxide sacrificial layer; a polysilicon membrane with an oxide sacrificial layer; and a nitride membrane with a polysilicon sacrificial layer. Three vacuum sealing mechanisms are compared, each of which requires a different degree of lithographic sophistication, uses a particular sealing mechanism, and results in a sealed cavity. Submicrometer via sealing requires sophisticated lithography but is amenable to LPCVD nitride, LTO, and other sealing procedures. Standard g-line lithography results in vies which seal only with high sticking coefficient species, such as LTO. A novel etch channel structure, which results in lateral sealing and requires neither sophisticated lithography nor a particular sealing material, is demonstrated. Finally, the impact of electrode metallization on the impedance, bandwidth, and efficiency of the transducers is discussed. The experiments in the paper are guided by theoretical analysis and computer simulations when applicable. The new process results in optimized devices which have a broad-band 50-/spl Omega/ real part impedance in the megahertz range. A transducer dynamic range in excess of 100 dB is achieved around 4.5 MHz. An untuned transducer exhibits more than 100% bandwidth when connected to electronics with 50-/spl Omega/ input impedance. In addition, beam pattern measurement shows the immersion devices behave like uniform piston transducers and are readily suitable for array applications. The fabrication techniques and results herein reported indicate that surface micromachined ultrasonic immersion transducers are an attractive alternative to piezoelectric transducers in immersion applications.

Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates

For gate oxides thinner than 40 /spl Aring/, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer; we have grown 25 /spl Aring/ gate oxide and prevented B penetration in the presence of F after 90 min of 850/spl deg/C and 10 s of 1050/spl deg/C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFETs is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFETs is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B penetration also improves the short-channel effects for 0.25-/spl mu/m pMOSFETs, while no difference is seen in nMOSFETs with and without N implant.

Surface micromachined tuneable interferometer array

The development of compact light modulators integrated on the same chip as the signal processing opens many opportunities for combining inter-chip optical communications with standard silicon circuitry. The use of surface micromachining allows high speed of operation and small size integration with other circuitry. The optical and mechanical requirements for the devices also have to be considered, to ensure compatability with standard silicon processing. A surface micromachining process, using an oxide sacrificial layer and poly/nitride/poly membranes, has been developed. This paper presents the optical and mechanical considerations in the development of a compact micromachined silicon Fabry-Perot interferometer. Initial tests have shown that these micromachined membranes represent a compact and effective light modulating method.

Electric micromotors on silicon

A review of micromotor technology will be presented and micromotor design, fabrication, and operational characteristics will be discussed. Micromotors are submillimeter actuators capable of unrestrained motion in at least one degree of freedom. The micromotors described in this presentation are actuated by attractive electrostatic forces. For micromotor fabrication, silicon surface micromachining is used to create freely moving parts held to the surface of the silicon wafer with bearings. In this process, heavily phosphorus-doped polysilicon is used for the structural parts, deposited silicon dioxide is used for the scarificial layers, and silicon-rich silicon nitride is used for electrical isolation. Layers of the structural and sacrificial materials are deposited and patterned in a manner that the structural polysilicon parts (e.g., the rotor) are appropriately encapsulated by the sacrificial oxide layers. At the final stage of fabrication, the sacrificial oxide is selectively removed in hydrofluoric acid to free the micromotor structural parts. Operational rotary, variable-capacitance, salient-pole, and harmonic (or wobble) side-drive micromotors have been fabricated with two different bearing designs and typical diameters of 100- to 130-μm, rotor/stator gaps of 1.5 μm, and a rotor thickness of 2.2 μm. Electrical operation of the salient-pole and harmonic side-drive micromotors have been demonstrated in a number of gaseous environments including room air, oxygen, argon, and nitrogen, and in insulating liquids such as silicone lubricating oil and deionized water. Minimum operating voltages differ with the environment but can be as low as 30 V. Extended operation (i.e., beyond 100 h) of the micromotors in gaseous environments and in silicone lubricating oil has been demonstrated. Operational speeds of up to 15 000 and 1000 rpm have been achieved in gaseous environments for the salient-pole and harmonic side-drive micromotors, respectively. In silicone lubricating oil, the maximum operation speed has been below 125 rpm for both micromotor types. [The presentation reflects the results of a collaborative micromotor research program with Professor J. H. Lang and Professor S. D. Senturia of MIT. This research program is funded by the National Science Foundation.]

HF/Ethanol Preoxidation Silicon Cleaning: Analysis of the Silicon Surface and of the Ultra-Thin Oxide Layer

ABSTRACTThe HF/Ethanol cleaning treatment is analyzed in comparison to the HF/H 20 one. The surface analysis is made on <100> silicon wafers with sacrificial oxide layer and silicon wafers with different crystallographic orientation without sacrificial layer. The results deduced from Atomic Force Microscopy, X-ray Photoelectron Spectroscopy and ellipsometry, show that siliconfluorine bonds are related with reactive sites. The structure of the thermally thin oxide layer grown after both cleanings has been analyzed and the electrical measurements show better performance for the HF/Ethanol cleaning.

Comparison between Air and UV/Ozone Surfaces Passivation Methods of GaAs (100) Substrates

ABSTRACTAir and UV/ozone exposure have been used for growing sacrificial thin oxide layers on HCl etched GaAs (100) surfaces. Passive films have been then desorbed by vacuum thermal cleaning in order to prepare suitable surfaces for molecular beam epitaxy (MBE) growth. Structure, thickness and chemical composition of passive films and desorbed surfaces have been studied by ellipsometry and angle dependent X-ray photoelectron spectroscopy (ADXPS). The results have indicated an increased chemical reactivity of both arsenic and gallium during UV/ozone exposure, compared to that of air exposure, that produces Ga (III) oxide enriched films. Furthermore, XPS results have also shown that the thermal desorption behavior are different. In particular, GaAs (100) after short term UV/ozone exposure and oxide film desorption, has an As/Ga surface atomic ratio close to unity and a level of carbon contamination below the XPS detectability. On the contrary, air exposed surfaces never have a stoichiometric composition and carbon is not completely removed by a vacuum heating.

XPS investigation on vacuum thermal desorption of UV/ozone treated GaAs(100) surfaces

In order to prepare suitable surfaces for molecular beam epitaxy (MBE), sacrificial thin oxide layers on HCl etched GaAs(100) surfaces were grown by both air and UV/ozone exposure. Passive films were subsequently removed by vacuum thermal desorption to achieve surfaces that were smooth and clean on an atomic scale. The evolution of the surface chemical composition, as a function of vacuum desorption temperature, has been studied by means of X-ray photoelectron spectroscopy (XPS). XPS results have evidenced for air and UV/ozone exposed GaAs(100) surfaces a relationship between desorption temperature and surface chemical composition; indeed, the oxide removal is temperature dependent and sequentially selective as follows: As 2O 3. AsO and Ga 2O 3. Furthermore, XPS results have shown that air-grown films have a chemical composition and thermal desorption behaviour different from UV/ozone treated materials. Indeed, these latter have an As 2O 3/Ga 2O 3 and an unoxidized As/Ga ratio close to unity for as grown and thermal treated at 580°C surfaces, respectively. By contrast, air-exposed GaAs(100) materials are Ga 2O 3-enriched and after vacuum thermal desorption treatments have never a stoichiometric composition(As (GaAs)/Ga (GaAs)= 1). Furthermore UV/ozone treated GaAs(100) surfaces subjected to a vacuum thermal treatment at 580°C, have a troublesome organic contamination level below XPS detectability, whereas from air-exposed surfaces, carbon is not completely thermally removable