Overlay Metrology Research Articles

Enhancement of Diffraction-Based Overlay Model for Overlay Target With Asymmetric Sidewall

Overlay metrology is crucial to process control in manufacturing semiconductor devices. Diffraction-based overlay (DBO) is an effective overlay measurement approach because it exhibits multiple advantages. This study analyzed measurement errors caused by sidewalls in the bottom gratings of DBO targets. Accordingly, improvement was proposed using a neural network. First, rigorous coupled wave analysis was employed to calculate the pupil images generated by an overlay target. These images were then used as a data set. Next, two-directional twodimensional principal component analysis was used to reduce the dimension of features in these images. The features were then used to train a neural network and determine weighting coefficients in each network layer to create a DBO model. This study used virtual metrology to analyze 30 types of overlay targets and generated 18900 pupil images to create a data set. Each overlay target model was measured 10 times, and shot noise, dark noise, and quantization noise in the pupil images were accounted for. The simulation results revealed that when the dose level was 1000 mJ/s·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the overlay mean square error of the testing data was 0.40nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , indicating notable improvement in the measurement results of overlay targets with bottom grating sidewalls. Therefore, the proposed neural network-based DBO model can be applied to overlay targets with sidewalls and effectively improve the overlay accuracy.

Multiobjective optimization for target design in diffraction-based overlay metrology.

Overlay target design is an important issue in overlay metrology, whose aim is to probe the optimal overlay target to achieve good performance on measurement precision and accuracy even in the presence of process variation. In this paper, the target design problem is first formulated as a multiobjective optimization problem and then solved by the multiobjective genetic algorithm. The feasibility of the proposed method is verified based on simulations carried out on two overlay targets. The results reveal that measurements with high precision, accuracy, and process robustness could be achieved on the targets designed by the proposed method.

Selection of DBO measurement wavelength for bottom mark asymmetry based on FDTD method

A physical model for simulating overlay metrology employing diffraction based overlay (DBO) principles is built. It can help to optimize the metrology wavelength selection in DBO. Simulation result of DBO metrology with a model based on the finite-difference time-domain (FDTD) method is presented. A common case (bottom mark asymmetry) in which error signals are always induced in DBO measurement due to the process imperfection were discussed. The overlay sensitivity of the DBO measurement across the visible illumination spectrum has been performed and compared. After adjusting the model parameters compatible with the actual measurement conditions, the metrology wavelengths which provide the accuracy and robustness of DBO measurement can be optimized.

Overlay error investigation for metal containing resist

Metal containing resists (MCR) are one of the candidates for extreme ultraviolet resists aiming to achieve the resolution, linewidth roughness, and sensitivity requirements of advanced design nodes. MCRs intrinsically have high etch resistance owing to their metal content. Therefore, low resist thickness (∼18 nm) is sufficient to transfer resist patterns into an underlying hard mask. Also, the thin resist reduces susceptibility to pattern collapse during development because of low aspect ratio. However, thus far, little attention has been paid to optical metrology and inspectability (overlay, defect inspection, scatterometry, etc.) of these resists, which is another critical requirement to move MCR toward high-volume manufacturing. We investigate the overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR), it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

Marker Layout for Optimizing the Overlay Alignment in a Photolithography Process

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms.

Overlay error statistics for multiple-exposure patterning

Background: The mathematical equations that explain overlay error of multiple-exposure patterning schemes have not been fully described in the literature and some commonly accepted methods lead to inaccurate estimated and/or measured overlay error. Aims: Develop the proper mathematical framework, using a first principles statistical approach, so that engineers using multiple-exposure patterning can determine the overlay impact and overlay controls needed. Alert patterning community that grouped overlay metrology of multiple-exposures undermeasures the true overlay error. Approach: Use image placement error and population-based statistics to enable a mathematical framework to be established that predicts the actual overlay error for an overlaying pattern that minimizes overlay error back to a pattern that is patterned with multiple-exposure patterning. Results: The overlay error between two patterns is usually less than the root sum square of the two overlay error values of the patterns individually measured to a common prior pattern. Overlay error for a pattern minimizing back to multiple-prior patterns increases quickly as systematic overlay error between the prior patterns increases. Conclusions: Controlling systematic overlay error between patterns of a multipatterned layer is important for subsequent patterns that need to minimize overlay error back to the composite multipatterned layer. The ratio between the overlay error determined with metrology and true overlay can be calculated.

A novel overlay metrology method: Simultaneous utilizing spectral and angular spectrum

In the lithography process, overlay describes the position errors of placing one mask layer pattern over an existing pattern on the wafer, and overlay metrology is one of the key challenges in semiconductor manufacturing. With the increase of process complexity especially for multiple patterning technologies in advanced nodes, the demand for accuracy, precision and process robustness in overlay metrology continues to tighten. In this paper, we have proposed and demonstrated a novel overlay metrology method with high process robustness. A straightforward theory called interference of diffraction light is developed for explanations why this method works for single layer overlay metrology. The overlay signals with continuous wavelengths and angles are simultaneously acquired in the pupil plane. Therefore, compared with the current monochrome measurement technology, this work can gather and utilize as much overlay information as possible for measurements. Experiments illustrate that this technique can achieve better measurement repeatability, faster measurement speed and better process robustness than current monochrome method, and thus this method has great potential to meet the higher node requirements for measurement accuracy. What’ more, our work provides a novel idea for scatterometry technology in the field of micro-nano measurement.

Robust overlay metrology with differential Mueller matrix calculus.

Overlay control is of vital importance to good device performances in semiconductor manufacturing. In this work, the differential Mueller matrix calculus is introduced to investigate the Mueller matrices of double-patterned gratings with overlay displacements, which helps to reveal six elementary optical properties hidden in the Mueller matrices. We find and demonstrate that, among these six elementary optical properties, the linear birefringence and dichroism, LB' and LD', along the ± 45° axes show a linear response to the overlay displacement and are zero when the overlay displacement is absent at any conical mounting. Although the elements from the two 2 × 2 off-diagonal blocks of the Mueller matrix have a similar property to LB' and LD', as reported in the literature, we demonstrate that it is only valid at a special conical mounting with the plane of incidence parallel to grating lines. The better property of LB' and LD' than the Mueller matrix elements of the off-diagonal blocks in the presence of overlay displacement verifies them to be a more robust indicator for the diffraction-based overlay metrology.

High-order distortion control using a computational prediction method for device overlay

As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.

New insights into subsurface imaging of carbon nanotubes in polymer composites via scanning electron microscopy

Despite many studies of subsurface imaging of carbon nanotube (CNT)-polymer composites via scanning electron microscopy (SEM), significant controversy exists concerning the imaging depth and contrast mechanisms. We studied CNT-polyimide composites and, by three-dimensional reconstructions of captured stereo-pair images, determined that the maximum SEM imaging depth was typically hundreds of nanometers. The contrast mechanisms were investigated over a broad range of beam accelerating voltages from 0.3 to 30 kV, and ascribed to modulation by embedded CNTs of the effective secondary electron (SE) emission yield at the polymer surface. This modulation of the SE yield is due to non-uniform surface potential distribution resulting from current flows due to leakage and electron beam induced current. The importance of an external electric field on SEM subsurface imaging was also demonstrated. The insights gained from this study can be generally applied to SEM nondestructive subsurface imaging of conducting nanostructures embedded in dielectric matrices such as graphene-polymer composites, silicon-based single electron transistors, high resolution SEM overlay metrology or e-beam lithography, and have significant implications in nanotechnology.

Nanoscale Magnification and Shape Control System for Precision Overlay in Jet and Flash Imprint Lithography

Jet and flash imprint lithography steppers have demonstrated unprecedented capability for patterning of sub-25-nm features for semiconductor manufacturing. A critical requirement for such patterning is the ability to overlay one layer of a device to a previously printed layer. In this paper, the design and development of a nanoprecision mask magnification/shape control system (MSCS) for the unique requirements of imprint-based overlay is presented. Imprint specific topics such as in-liquid overlay and distortions, and on-tool overlay metrology are discussed. The MSCS presented here has demonstrated 10-nm mix and match overlay (mean + 3 sigma) capability that approaches performance of state-of-the-art photolithography tools.

Techniques for improving overlay accuracy by using device correlated metrology targets as reference

The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.

Exact and reliable overlay metrology in nanoscale semiconductor devices using an image processing method

As semiconductor processing becomes more complicated and pattern sizes shrink, the overlay metrology has become one of the most important issues in the semiconductor industry. Therefore, in order to obtain correct, reliable overlay values in semiconductor fabrication facilities (fab), quantization methods for the efficient management and implementation of a measurement algorithm are required, as well as an understanding of the target structures in the semiconductor device. We implemented correct, reliable overlay values in the pattern using the image processing method. The quantization method, through correlation analysis and a new algorithm for target structures, were able to improve the sensitivity to misalignment in the pattern and enable more stable and credible in-line measurement by decreasing the distribution of the residuals in overlay values. Since overlay values of the pattern in the fab were measured and managed more reliably and quickly, it is expected that our study will be able to contribute to the yield enhancement of semiconductor companies.

Formulation of error propagation and estimation in grating reconstruction by a dual-rotating compensator Mueller matrix polarimeter

Recently, the Mueller matrix polarimeter (MMP) has been introduced for critical dimension and overlay metrology. In practice, the measurement process invariably has errors. These errors, which can be generally categorized into random and systematic errors, have great influences on the final precision and accuracy of the extracted structural parameters. In this paper, we present detailed formulations for the propagation and estimation of random and systematic errors in grating reconstruction using a dual-rotating compensator MMP (DRC-MMP). We derive a generalized first-order error propagating formula, which reveals the mechanism of error propagation in grating reconstruction using the DRC-MMP. According to this first-order error propagating formula and the measurement principle of the DRC-MMP, we then derive detailed formulations for the estimation of random and systematic errors that are propagated into the final extracted structural parameters. Simulations performed on silicon grating samples have demonstrated the validity of the present theoretical derivations.

Infrared differential interference contrast microscopy for 3D interconnect overlay metrology

One of the main challenges for 3D interconnect metrology of bonded wafers is measuring through opaque silicon wafers using conventional optical microscopy. We demonstrate here the use infrared microscopy, enhanced by implementing the differential interference contrast (DIC) technique, to measure the wafer bonding overlay. A pair of two dimensional symmetric overlay marks were processed at both the front and back sides of thinned wafers to evaluate the bonding overlay. A self-developed analysis algorithm and theoretical fitting model was used to map the overlay error between the bonded wafers and the interconnect structures. The measurement accuracy was found to be better than 1.0 micron.

Substrate Induced Overlay Non-Uniformity Study

According to ITRS roadmap, the overlay control becomes more and more critical with the layout design shrinkage. In order to meet the tight overlay requirement lots of new techniques had been proposed from exposure system, metrology equipment and APC algorithm. Although current overlay techniques can obviously improve overlay control capability, they still cannot include all factors which will impact overlay into the model. To describe the impact from those factors which are not involved in model, the model fitting error is introduced. Normally it is not so important in generic logical process. But it will become very serious and lead to terrible yield loss in some special case. In all kinds of factors which impact to overlay, the wafer substrate and thermal process are seldom reported, but actually both of them are critical or fatal factors of overlay fail in high voltage and high power devices which have lots of high temperature thermal process. In this paper, we will demonstrate the overlay non-uniformity study with different substrates, film stacks, thermal processes and EPI processes. Seriously random occurrence of overlay non-uniformity is found and the model fitting error is very large. It cannot be resolved by typical overlay improvement method such as overlay mark design, alignment detecting, overlay metrology method and APC algorithm refine. Splits on wafer substrate, thermal and EPI process are proposed. Finally the non-uniformity is reduced by over 90% and model fitting error is also largely reduced.

Critical dimension scanning electron microscope local overlay measurement and its application for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using a critical dimension scanning electron microscope (CD-SEM), which can be applied to two-dimensional (2D) device structures such as a static random access memory contact hole array. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the optical overlay. The methodology includes the use of pattern symmetry to cancel out many process effects and reduce measurement uncertainty. CD-SEM overlay metrology was compared with conventional optical overlay metrology in terms of measurement uncertainty and overlay model analysis, and very good correlation was confirmed. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. The local overlay distribution was obtained across the device area, and spatial correlation of the overlay error vectors was examined over a large range of distances. The applications of CD-SEM overlay metrology were explored, and methodologies were introduced to examine both the overlay of double patterning contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical CD-SEM overlay metrology was introduced in order to capture a high order, device weighted overlay response.

New approaches for scatterometry-based metrology for critical distance and overlay measurement and process control

mmunication between lithography and metrology is becoming increasingly demanding in advanced nodes. This is where the requirements for metrology become extremely tight. This work is dedicated to the search for clean metrology that is required to address these requirements. Metrology measurements are obtained via an angle-resolved scatterometry-based platform (called YieldStar). Details of the technology behind YieldStar were thoroughly discussed by Vanoppen et al. in 2010. In this current work, measurement limits are challenged to test resolution and measurement uncertainty for overlay, critical dimension (CD), and sidewall angle (focus). Results indicate an atomic-scale performance of deep subnanometers. Two different sizes of scatterometry-based overlay targets are evaluated and compared using a technique called the similarity index. A CD reconstruction model is tested for cross talk of underlying thin-film layers, specifically the case where one of the underlying layers is anisotropic. A systematic approach is taken to increase the complexity of a CD reconstruction model in steps to evaluate the capability of handling birefringence effects of anisotropic material in the model. CD metrology data (1-D and 2-D/hole layers) are compared to CD scanning electron microscope data. Focus measurements are also extended for product wafers, and focus precision is evaluated. In addition, CD metrology monitor wafer applications, such as hotplate monitoring and overlay metrology monitor wafer application for scanner stability and matched machine overlay, are tested.

Subnanometer-accuracy z-position monitor mask for optical lithography

A lithographic test pattern, the phase shift grating (PSG) z monitor, is introduced. Through the use of phase shift techniques, position errors of images in the z-direction translate into lateral shifts in the printed pattern. The lateral shifts are easily measurable using an overlay metrology tool. Each z monitor pattern in a test mask can be directly read for the sign and magnitude of the z error. When the experimental conditions, namely, the period of a PSG and a coherent factor of the lithography tool simultaneously satisfies a criterion of the asymmetric two-beam interference between the zeroth-order ray and either of the two first-order rays of diffraction, the linearity of a z-vs-overlay curve is always complete and the slope of the curve is constant everywhere in the image field. Using state-of-the-art overlay metrology tools, we realized subnanometer-order accuracy in the z measurement.