The impact of oxygen in silicon substrates and the formation of oxide precipitates have been widely investigated in the past, because of deleterious electrical recombination and their impact on yield [1]. The presence of oxygen can also be beneficial, with the so-called internal gettering effect by oxygen precipitates. More recently, researchers pointed out the role of interstitial oxygen on the formation of slip lines and dislocations [1-2]. The impact of interstitial oxygen during thermal treatments has to be distinguished from the one of oxygen precipitates for a better understanding of various phenomena [3]. We show in this paper the combined impact of features such as interstitial oxygen, thermal processes and innovating SOI substrates on slip-line generation after complex device fabrication process flows.We have investigated different kinds of silicon and SOI substrates (with silicon obtained with the Czochralski method) that were submitted to different thermal treatments during a specific 65nm process flow targeting Radio-Frequency devices. We have worked on 300mm patterned and blanket wafers and focused notably on a last stressing oxidizing anneal step used for gate oxide formation. One type of SOI substrates had a poly-silicon layer beneath the buried oxide (named SOI Trap-Rich) specifically for RF applications [4]. We have used two kinds of processes, low and high temperature, in Rapid Thermal Oxidation (RTO) tools. Slip-line counts and cumulated lengths were monitored on blanket SOI and Si wafers after main anneal steps and gate oxide RTO, using a Pattern Wafer Geometry (PWG) tool (figure 1). The post-nitridation anneal for gate oxide formation was performed at temperature above 1000°C in single wafer tools. On Si and SOI with 70nm-thick Si layers, no slip-lines were detected using Process-Of-Record conditions (whatever the process temperature). Meanwhile, high temperatures and above all extreme edge offset temperatures (usually used in single wafer reactors to have processes as uniform as possible) resulted in higher slip-line counts and cumulated lengths on the wafers back-sides. On SOI with TR layers, slip-lines were detected whatever the conditions, although they were less numerous with a low temperature and optimized process.Differences for wafers processed at the same time highlighted the influence of several parameters: the thermal history evidenced by wafer-to-wafer variability for SOI wafers with a Trap-rich layer underneath, the stack (SOI type and nature) and the process temperature used during previous oxidation steps. A typical map obtained by the PWG is shown in Figure 2 [5]. Meanwhile, Figure 3 shows a macro Photoluminescence mapping of a blanket Silicon wafer, pointing out the electrical activity of planar defects at the wafer edges (non-radiative recombination on dislocations). A direct relationship was found between the slip-line origin and contact points coming from ring supports at wafers’ back-side (the origins of slip lines). Figure 4 shows the relationship between the oxygen concentration in bulk Si and the silicon handles of SOI substrates, the slip-line counts and wafer warp. Based on this trend, we have also statistically confirmed on patterned wafers processed in a 65nm RF flow, the direct relationship between substrate deformation, low oxygen concentration in the Si handle (lower at wafer edge in agreement with slip line formation) and lithography overlay (OVL) measurements. When OVL exceeded a certain value, residuals (i.e. misalignments due to shifts between patterns which are symbolized by vectors) could not be corrected any more. It is typically what we have on SOI TR substrates with an extreme offset temperature (intentionally too high). An OVL signature out of our range of specifications is shown in Figure 5 on a patterned wafer processed up to gate oxide level. High numbers of slip lines result in OVL over detection. Meanwhile, wafer deformations and more precisely stresses that are too high increase OVL residuals. Above a given threshold, the built-in stress in the wafer is so high that slip lines are nucleated at the wafer edges to minimize the elastic energy. Above a second threshold, the wafer deformation is irreversible. Finally, the relationship between OVL and electrical failure is not straightforward and more often the consequence of mixed parameters such as substrate composition and nature, annealing steps and etching during Shallow Trench Isolation or gate oxide definition.[1] J. Fujise et al, Japanese J. of Applied Physics, 57 (035501) 2018[2] J. Fujise et al, J. Solid State Science and Techn., 9 (055012) 2020[3] G. Kissinger et al, J. Solid State Science and Techn., 8 (N79) 2019[4] B.K. Esfeh et al, Solid State Electronics, 128 (121) 2017[5] V. Brouzet et al, ASMC conference, april 2019 Figure 1
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Oct 3, 2024
Hung-Chih Hsieh + 2
Open Access