Abstract

Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality.

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