Abstract
This paper presents a novel method for control of overlay errors in photolithography processes in semiconductor manufacturing. It minimizes the largest overlay error across all measurement markers on a pattern layer, and this minimization is done for the worst-case scenario regarding bounded process bias and modeling noise terms. This large-scale robust optimization problem was formulated as a linear program which can be solved within seconds to generate optimal control commands. Simulations based on wafer data obtained from a major 300 mm semiconductor fab illustrate consistent and significant advantages of this approach over the benchmark control strategies.
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